VLSI Research Articles

Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure

In this paper, a power-efficient self write-terminated hybrid full-adder (SWTHFA) has been developed using the self write-terminated write driver and an improved version of the sense amplifier already reported in the literature. The SWTHFA is designed using hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuit based on logic-in-memory architecture. The use of a modified sense amplifier improves the power dissipation and output response on one hand, whereas, on the other hand, self-write-terminated write driver cuts off the unnecessary flow of write current in the driver circuit, thereby eliminates power wastage in SWTHFA. Proposed SWTHFA shows improvement in power saving, output response, read and write power delay product by 38.87%, 26.45%, 40.86% and 36.53%, respectively, compared to conventional write hybrid full-adder (CWHFA). Further, we performed Monte-Carlo simulations by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ to demonstrate the feasibility of SWTHFA in low-power VLSI circuits.

Mixed analog–digital method of designing a heterogeneous network with the desired collective behavior and rapid convergence

Among many advances given by the diffusive coupling on the synchronization problem, recently a design method for a continuous-time heterogeneous network with the desired collective behavior has been developed. Meanwhile, by its use of high-gain, implementation issues arise in discrete-time frameworks. The goal of this paper is thus to introduce a simple scheme that follows the philosophy of Carver Mead, a pioneer of VLSI (Very Large Scale Integration) technology, that removes those implementation issues. In the end, we utilize what corresponds to derivative consensus in continuous-time, which can be realized by, for instance, an analog electric circuit. This provides a mixed analog–digital method of designing a heterogeneous network with the desired collective behavior and rapid convergence.

Analytical Modeling of Short-Channel TMD TFET Considering Effect of Fringing Field and 2-D Junctions Depletion Regions

An analytical drain current model is developed for a short-channel, dual-gate, monolayer 2-D transition metal dichalcogenide (TMD), lateral tunnel field-effect transistor (TFET) by considering 2-D <inline-formula> <tex-math notation="LaTeX">${p}^{+}-{n}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${n}-{n}^{+}$ </tex-math></inline-formula> junction at source&#x2013;channel and channel&#x2013;drain junction, respectively. This work includes the effect of both front- and back-gate dielectric fringing field effects and 2-D source and drain depletion charges. A unified piecewise surface potential model is developed by capturing the fringing field effects in the channel and 2-D junction behavior at the source&#x2013;channel and channel&#x2013;drain junction by ensuring continuity of electric field at the junction regions. A tangent-line approximation method is employed for accurate numerical evaluation of the tunneling current. The proposed model is validated with simulation results obtained using nonequilibrium Green&#x2019;s function (NEGF)-based simulator for different 2-D layered materials and a close agreement is observed. The veracity of the proposed model is tested with data in reported studies for different bias conditions and excellent matching is observed. The applicability of the model is demonstrated for any 2-D layered material-based TFET from ultrashort channel to a channel length of 50 nm. The proposed model will be extremely useful for further exploration of 2-D TMD material TFET-based very large-scale integration (VLSI) circuits.

Measurement of single event effect cross section induced by monoenergetic protons on a 130 nm ASIC

Designing integrated circuits in radiation environments such as the High Luminosity LHC (HL-LHC) is challenging. Integrated circuits will be exposed to radiation-induced Single Event Effects (SEE). In deep sub-micron technology devices, the impact of SEEs can be mitigated by triple modular redundancy. The triplication of the most sensitive data is used to recover most of the data corruption induced by interacting particles. One type of SEE, called single event upset (SEU), is studied in this paper. The SEU cross-section and the performance of the triplication are estimated using an ASIC prototype exposed to a beam of protons. The SEU cross-section is measured and systematic difference between 1→0 and 0→1 bit flip rates is observed. The efficiency of the mitigation method is investigated.

Self-Aligned Double Injection-Function TFT for Deep Sub-Micrometer Channels’ Length—Application to Solution-Processed Indium Gallium Zinc Oxide

We propose and demonstrate self-aligned Double Injection Function Thin Film Transistor (DIF-TFT) architecture that mitigates short channel effects in 200 nm channel on non-scaled insulator (100 nm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). In this conceptual design, a combination of ohmic-like injection contact and a high injection-barrier metal allows maintaining the high ON currents while suppressing drain-induced barrier lowering (DIBL) effects. Using an industrial 2-D device simulator (Sentaurus), we propose two methods to realize the DIF concept. We use one of them to demonstrate, experimentally, a DIF-TFT based on solution-processed indium gallium zinc oxide (IGZO). Using molybdenum as the ohmic contact and platinum as the high injection barrier, we compare three transistors’ source-contacts: ohmic, Schottky, and DIF. The fabricated DIF-TFT exhibits saturation at sub 1 V drain bias with only about a factor of 2 loss in ON current compared to the ohmic contact.

Modification and Characterization of Interfacial Bonding for Thermal Management of Ruthenium Interconnects in Next-Generation Very-Large-Scale Integration Circuits.

Ruthenium may replace copper interconnects in next-generation very-large-scale integration (VLSI) circuits. However, interfacial bonding between Ru interconnect wires and surrounding dielectrics must be optimized to reduce thermal boundary resistance (TBR) for thermal management. In this study, various adhesion layers are employed to modify bonding at the Ru/SiO2 interface. The TBRs of film stacks are measured using the frequency-domain thermoreflectance technique. TiN and TaN with high nitrogen contents significantly reduce the TBR of the Ru/SiO2 interface compared to common Ti and Ta adhesion layers. The adhesion layer thickness, on the other hand, has only minor effect on TBR when the thickness is within 2-10 nm. Hard X-ray photoelectron spectroscopy of deeply buried layers and interfaces quantitatively reveals that the decrease in TBR is attributed to the enhanced bonding of interfaces adjacent to the TaN adhesion layer, probably due to the electron transfer between the atoms at two sides of the interface. Simulations by a three-dimensional electrothermal finite element method demonstrate that decreasing the TBR leads to a significantly smaller temperature increase in the Ru interconnects. Our findings highlight the importance of TBR in the thermal management of VLSI circuits and pave the way for Ru interconnects to replace the current Cu-based ones.

Analysis of the Impact of Electrical and Timing Masking on Soft Error Rate Estimation in VLSI Circuits

Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptible to radiation-induced hazards such as soft errors. Thus, to design radiation-hardened and reliable ICs, the Soft Error Rate (SER) estimation constitutes an essential procedure. An accurate SER evaluation is provided based on a SPICE-oriented electrical masking analysis, combined with a TCAD characterization process. Furthermore, the proposed work analyzes the effect of a Static Timing Analysis (STA) methodology and the actual interconnection delay on SER evaluation. An analysis of the generated Single Event Multiple Transients (SEMTs) and the circuit operating frequency that are related to the SER estimation is also discussed. Various benchmarks, synthesized utilizing a 45 nm and 15 nm technology, are employed, and the experimental results demonstrate the SER variation as the device node scales down.

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

A Theoretical Modeling of Adaptive Mixed CNT Bundles for High-Speed VLSI Interconnect Design

The aroused quest to reduce the delay at the interconnect level is the main urge of this paper, so as to come across a configuration of carbon nanotube (CNT) bundles, namely, squarely packed bundles of mixed CNTs. The demonstrated approach in this paper makes the mixed CNT bundle adaptable to adopt for high-speed very-large-scale integration (VLSI) interconnects with technology shrinkage. To reduce the delay of the proposed configuration of the mixed CNT bundle, the behavioral change of resistance (R), inductance (L), and capacitance (C) has been observed with respect to both the width of the bundle and the diameter of the CNTs in the bundle. Consequently, the performance of the modified bundle configuration is compared with a previously developed configuration, namely, squarely packed bundles of dimorphic MWCNTs in terms of propagation delay and crosstalk delay at local-, semiglobal-, and global-level interconnects. The proposed bundle configuration is, ultimately, enacted as the better one for 32-nm and 16-nm technology nodes, and is suitable for 7-nm nodes as well.

6T and 8T SRAM Cell Simulation with Power Loss Analysis

Reducing the power consumption in a VLSI circuits is a prime concern now a days. Memory circuits play an important role in the design of electronic small power devices. Almost every digital systems is having memory as an important part in their design. The high speed circuits dissipate a considerable amount of power in a short time. In this paper conventional SRAM cell is modified little bit to reduce the dynamic power dissipation. The overall capacitance reduced by adding few extra transistors. Because of the fact that charging and the discharging of the bit lines consumes the most power , so 6T cell and 8T cell can be used to reduce the power by adding an extra number of transistors to the pull down path. In this paper 6T SRAM cell as well as 8T SRAM cell simulated and their performance compared in terms of power dissipation.

An efficient and cost effective application mapping for network-on-chip using Andean condor algorithm

Advancement in very large scale integration (VLSI) technologies and the ever-shrinking size of the transistors have led the semiconductor designers to create a multiprocessor system on chips. Network on chip (NoC) provides an efficient and flexible communication infrastructure to these systems. One of the most prominent research problems in NoC is mapping the real-time application tasks to multiple cores. The aim is to map the cores, which require frequent and high-bandwidth communications close enough to increase the performance and decrease the chip’s power consumption. In this research, a nature-inspired Andean condor algorithm (ACA) is applied to the mapping problem of application tasks on multiple cores of NoC. Initially, a clustering-based technique provides the main algorithm a head-start for fast convergence, and then the main ACA is applied to achieve the optimal performance. The simulation results show that the proposed algorithm outperformed state-of-the-art algorithms in terms of various performance metrics, such as communication cost, average packet latency, throughput and energy consumption. The proposed algorithm achieves up to 27.11% improvement in communication cost and provides 78.9% savings in computational overhead.

An Efficient Delay Estimation Model for High Speed VLSI Interconnects

In this paper a closed-form matrix rational model for the computation of step and finite ramp responses of Resistance Inductance Capacitance (RLC) interconnects in VLSI circuits is presented. This model allows the numerical estimation of delay and overshoot in lossy VLSI interconnects. The proposed method is based on the U-transform, which provides rational function approximation for obtaining passive interconnect model. With the reduced order lossy interconnect transfer function, step and finite ramp responses are obtained and line delay and signal overshoot are estimated. The estimated delay and overshoot values are compared with the Euder method, Pade method and HSPICE W- element model. The 50% delay results are in good agreement with those of HSPICE within 0.5% error while the overshoot error is within 1% for a 2 mm long interconnect. For global lines of length more than 5 mm in SOC (system on chip) applications, the proposed method is found to be nearly four times more accurate than existing methods.

VLSI Implementation of DENLMS Adaptive Filter for Biomedical Applications

Very Large Scale Integration (VLSI) implementation of the Delayed Error Normalized LMS (DENLMS) adaptive filter using a pipelined architecture is proposed and it can be used for biomedical applications. The proposed pipelined VLSI architecture increases the performance of adaptive filters by lowering the amount of time spent on critical path calculation. When compared to the current Error Normalized Least Mean Square (ENLMS) method for pipelining purposes, the DENLMS technique requires an additional delay element, and because of the delay element, the algorithm functions faster and more effective in low-power applications. The proposed pipelined architecture of the DENLMS filter, on the other hand, improves the efficiency while consuming less power overall. The cell leakage power reduction and total dynamic power reduction obtained by using the DENLMS filter are 31.8% and 33.5%, respectively, although the overall area of the filter has increased by 20.4%.

Adaptive Multicale Transformation Run-Length Code-Based Test Data Compression in Benchmark Circuits

Test data volume reduction and power consumption during testing time outlines are two main problems for Very Large Scale Integration (VLSI) gadgets. Most the code-based arrangements have been utilized to diminish test data volume, although the most notable way that test data volume is high. The switching action that happens between the test carriers leads would expand power consumption. This work presents a compression/decompression methodology for limiting the amount of test data that should be kept on a tester and conveyed to each center in a System on a Chip (SOC) during a test utilizing the Adaptive Multiscale Transformation Run Length Code (AMT-RLC). The data transmission capacity between the tester and the SOC is a block when testing modern SOCs with a few centers to check how long the test can run. The proposed work keeps the tester in the SOC and the test vectors in a compacted memory structure. A modest quantity of On-chip equipment is needed to release different test vectors. Due to its variouscharacteristics that decrease the test data volume, the Adaptive Multiscale Transformation Run Length Code is picked for a center test vector framework. These attributes ensure that the code words overhead is decoded (and applied to the center's output exhibit grouping commitment) utilizing an exact cell cluster that occupies less space. The suggested strategy may provide test data compression with much-reduced Area overhead for the decoder and low power consumption, according to the results. The abstract shall be running continuously (not structured) and shall not include reference citations. Abbreviations should be defined in full the first time they appear. Abbreviations could be then used, quoted in-between parentheses.

A Radial Basis Function Network-Based Surrogate-Assisted Swarm Intelligence Approach for Fast Optimization of Power Delivery Networks

The design and optimization of Power Delivery Networks (PDNs) in Very Large Scale Integration (VLSI) systems is becoming very challenging with the increasing complexity of such systems. Decoupling capacitors are the key elements used in a PDN to minimize power supply noise and to maintain low impedance of the PDN to avoid system failure. In this paper, a novel approach using surrogate assisted swarm intelligence is presented for efficient and fast optimization of power delivery networks. For generating the surrogate models, a standard Radial Basis Function Network (RBFN) is used. Using the proposed approach, the decoupling capacitors are selected and placed optimally, eventually reducing the cumulative impedance of the PDN below the target impedance. The performance comparison between the conventional and the surrogate-assisted approach is presented. Three case studies are presented on a practical system to demonstrate the competence of the proposed approach. The results obtained by the proposed approach are also compared with the same obtained by the state-of-the-art approaches. For the proposed approach the run time is drastically reduced compared to the state-of-the-art approaches for the optimization problem without having any effect on the performance. The consistency of results in all of the case studies confirms the validity of the proposed approach.

Incredible VLSI Design for MIMO System Using SEC-QPSK Detection

Multiple Input Multiple Output (MIMO) is an advanced communication technology that is often used for secure data transfer for military and other applications while transmitting data with high error and noise. To address this issue, a step-by-step hybrid Quadrature Phase Shift Keying (QPSK) modulation scheme in the MIMO system for a complex Very Large-Scale Integration (VLSI) format is recommended. When compared to Binary Phase Shift Keying (BPSK), this approach provides twice the data rate while using half the bandwidth. The complexity is lowered through multiplication and addition, as well as error and noise reduction in data transport, and MIMO detection is accomplished through the combination of two techniques, Inverse Fast Fourier Transform (IFFT) and Stepwise Exponential Companding (SEC). IFFT converts frequency to the time domain, reducing complexity by 23.56 percent in multiplication and an extra 34.05 percent. Likewise, hierarchical high-speed mixing decreases difficult limits by 13% and the addition problem by 25%. This technological outcome results in a decreased Signal-to-Noise Ratio (SNR) and Bit Error Rate (BER).

Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling

A Trusted Execution Environment (TEE) sets a platform to secure applications based on the Chain-of-Trust (CoT). The starting point of the CoT is called the Root-of-Trust (RoT). However, the RoT implementation often relies on obscurity and provides little flexibility when generating keys to the system. In this paper, a TEE System-on-a-Chip (SoC) architecture is proposed based on a heterogeneous design by combining 64-bit Linux-capable processors with a 32-bit Micro-Controller Unit (MCU). The TEE is built on the 64-bit cores, while the 32-bit MCU takes care of sensitive data and activities. The MCU is isolated from the TEE side by an Isolated Bus (IBus) that sits above the conventional System Bus (SBus). Besides the 32-bit processor, the isolated sub-system contains a Random Access Memory (RAM), a Read-Only Memory (ROM) for storing the boot program, and another ROM for storing root keys. For cryptography accelerators, we have 512-bit Secure Hashing Algorithm 3 (SHA3-512), 128/256-bit Advanced Encryption Standard (AES-128/256), Ed25519, and True Random Number Generator (TRNG) attached to the Peripheral Bus (PBus). Additionally, besides the public channel, the TRNG module also has a private channel that goes directly to the IBus. With RoT implemented inside the isolated sub-system, the RoT is inaccessible from the TEE side after boot. Furthermore, the hidden MCU’s secure boot program makes the key generation flexible and could be updated for many security schemes. To summarize, the proposed design features a flexible and secure boot procedure with complete isolation from the TEE domain. Moreover, exclusive secure storage for the root key and cryptographic accelerators are available for the boot process. The implementation was tested on a Virtex-7 XC7VX485T Field-Programmable-Gate-Array (FPGA). It was also synthesized in a Very Large-Scale Integrated (VLSI) circuit with the ROHM-180nm process library.

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. Network-on-Chip (NoC) is a scalable and promising interconnection solution used by MPSoCs to achieve high performance. Routing algorithms provide a path to a packet toward the destination. For this, these algorithms should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews the selection strategies used to reduce congestion in NoC and classifies them on the technique adopted to handle and propagate congestion information. Additionally, this paper provides the implementation and analysis details of some state-of-art selection methods.

Analysis of modified P-I-N tunnel FET architecture for applications in low power domain

Tunnel FET with a few modifications is studied here for use in low power VLSI circuits as a worthy replacement of MOS based devices. The conventional TFET structure with P-I-N architecture is modified in the present work with dual gates, front and back, to give better control over the tunnelling current passing through the channel. In the proposed architecture asymmetrical lengths are utilised for the back and front gates, which improves the control even further. An SiGe based highly doped P + pocket is inserted in the intrinsic channel near the source end to rise the ON current and to increase the ION/IOFF ratio. In this device low subthreshold slope (SS) and lower DIBL values are also observed. The oxide layer below both the gates are engineered to optimise the combination of high and low k dielectric, lengths, to obtain performance improvement. Device Simulation Tool Silvaco Atlas is used to design and simulate the proposed device. Optimisation is done for the device with regards to length of channel, dimensions of the channel pocket, underlap and overlap lengths of the gates. The device is also tested over a wide range of temperatures to come to the best possible architecture, which is described here. The proposed device is proven to be a worthy contender to replace MOSFET in future ultra-low power, CMOS compatible VLSI circuits.

Design and Analysis of High-Performance and Low-Power Quaternary Latch,Quaternary D Flip-Flop and XY Flip-Flop

Multiple-valued logic (MVL) circuits propose a number of possible improvements to current VLSI circuit designs. Forexample, serious difficulties with limitations on the number of connections between an integrated circuit and the outside world(pinout concern) and also the number of links within the circuit encountered in some VLSI circuit synthesis could be greatlyreduced if signals in the circuit could assume four or more states instead of only two. This research work shows a quaternarylogic-based latch, a level-sensitive flop, and an edge-sensitive flop. In most of the cases it is seen that a sequential digital circuitproduces two outputs which are complementary to each other. But in most of the designs, there is no need of having both theoutputs of the flip-flops, so one of the quaternary outputs can be removed from the circuit, resulting in a decrease in area andstatic power. In quaternary circuits, several power sources or a single power supply source are employed. Those that haveseveral sources of supply use less energy. In multiple-valued logic we need the design to have multiple logic levels, like inquaternary logic, GND is used for logic ‘0’, 1/3Vdd is used for logic ‘1’, 2/3Vdd is for logic ‘2’, and Vdd is for logic ‘3’. Themulti-Vdd design method is incompatible with the purpose of reducing the inter-chip and intra-chip connections. In order toresolve this, a capacitive divider network is used while designing. The QFF is demonstrated with the necessary simulationresults using LTSpice tool and the simulations are performed using 32nm technology file. Finally, a quaternary shift register isbuilt to demonstrate the applicability and appropriate operation of the proposed QFF in larger sequential circuits.