Virtual Output Queuing Research Articles

Round Robin based Arbitration Mechanism for Signaling Approach based Router Architecture

In Network-on-Chip the effectiveness of the network resource allocation is demonstrated by the flow control mechanism. There are two types of flow control mechanisms: buffered and bufferless. Compared to buffered flow control methods, buffer less flow control mechanisms are easier to use, need less power, and take up less space. When there are congestion and resource conflicts, it experiences higher packet loss and packet misrouting inside the network. A good buffered control mechanism useful as it overcomes the limitations of buffer less mechanism. There are numerous buffered and bufferless flow control methods available. In this paper, signaling-based Virtual Output Queue Router Arbiter Mechanism is used to explore credit-based flow control. This mechanism worked on new concept that is “stress value”. This information is generated in the form of credit whenever any input buffer has free space. Then, using this credit data, the node's stress value is determined. Free buffer space takes precedence over stress value if it is bigger. The stress value will increase if there is less available buffer space. To handle the congestion problem, the signaling block then sends this stress value to a neighboring router. To help the arbitrator make a more accurate decision, the crediting system constantly operates in tandem with arbitration.

Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer

This paper studies small to medium-sized monolithic switches for FPGA implementation and presents a novel switch design that achieves high algorithmic performance and FPGA implementation efficiency. Crossbar switches based on virtual output queues (VOQs) and variations have been rather popular for implementing switches on FPGAs, with applications in network switches, memory interconnects, network-on-chip (NoC) routers etc. The implementation efficiency of crossbar-based switches is well-documented on ASICs, though we show that their disadvantages can outweigh their advantages on FPGAs. One of the most important challenges in such input-queued switches is the requirement for iterative scheduling algorithms. In contrast to ASICs, this is more harmful on FPGAs, as the reduced operating frequency and narrower packets cannot “hide” multiple iterations of scheduling that are required to achieve a modest scheduling performance.Our proposed design uses an output-queued switch internally for simplifying scheduling, and a queue balancing technique to avoid queue fragmentation and reduce the need for memory-sharing VOQs. Its implementation approaches the scheduling performance of a state-of-the-art FPGA-based switch, while requiring considerably fewer resources.

A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router

Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used for fine-grain flow control and Quality of Service (QoS), yet it is the major contributor of area and power consumption. In this paper, we propose a hybrid buffer design with SRAM and Spin-Torque Transfer Magnetic RAM (STT-RAM) for NoC router leveraging a novel architecture combined Virtual Channel (VC) and Virtual Output Queuing (VOQ) to store congested and uncongested flow separately. Experiments demonstrates that the proposed scheme can achieve 11.8% network performance improvement and 32.9% power saving with only 8.2% area overhead degradation compared to conventional SRAM based buffer design.

High Throughput Scheduling Algorithms for Input Queued Packet Switches

The high-performance computing paradigm needs high-speed switching fabrics to meet the heavy traffic generated by their applications. These switching fabrics are efficiently driven by the deployed scheduling algorithms. In this paper, we proposed two scheduling algorithms for input queued switches whose operations are based on ranking procedures. At first, we proposed a Simple 2-Bit (S2B) scheme which uses binary ranking procedure and queue size for scheduling the packets. Here, the Virtual Output Queue (VOQ) set with maximum number of empty queues receives higher rank than other VOQ’s. Through simulation, we showed S2B has better throughput performance than Highest Ranking First (HRF) arbitration under uniform, and non-uniform traffic patterns. To further improve the throughput-delay performance, an Enhanced 2-Bit (E2B) approach is proposed. This approach adopts an integer representation for rank, which is the number of empty queues in a VOQ set. The simulation result shows E2B outperforms S2B and HRF scheduling algorithms with maximum throughput-delay performance. Furthermore, the algorithms are simulated under hotspot traffic and E2B proves to be more efficient.

Architecting a congestion pre-avoidance and load-balanced wireless network-on-chip

The communication performance over conventional long-distant routers cannot satisfy the requirements of future multi-core systems. Wireless Network-on-Chip (WiNoC) architecture with CMOS compatible transceivers is utilized to obtain significant improvement in on-chip data transfer for multi-core systems. The wireless routers (WRs) in WiNoC architecture provide wireless shortcuts to alleviate the latency of multi-hop communications. Despite the additional bandwidth of wireless shortcuts, the WRs are prone to congestion due to the limited number of wireless channels and the shared use of these channels under unbalanced load. On the other hand, network performance will be severely degraded when the presence of head-of-line (HOL) blocking. In this paper, we establish a congestion pre-avoidance and load-balanced wireless network-on-chip architecture. To implement such architecture in our network, firstly, we propose an dynamic XY-YX routing algorithm detour WR to pre-avoid the additional traffic flow of the wireless router; Secondly, the virtual output queue scheme is adopted to handle HOL blocking, and on this basis we design a wireless router micro-architecture; Finally, a threshold-based load-balanced mechanism is designed, which uses the number of buffered flit as a guideline to avoid unbalance load. Through system-level simulations, the results demonstrate that the proposed WiNoC architecture can mitigate negative effect of congestion in WR. And with appropriate hardware overhead, network transmission latency and network throughput are significantly improved.

Speculative Packet Dispatch for Virtual Output Queuing Architecture Using LSTM Recurrent Neural Network

Virtual Output Queuing (VOQ) is an architecture widely employed in modern networking products. Traffic from every ingress port is stored in a set of queues mirroring the structure of the egress ports. This architecture allows congestion on one egress port to be isolated from the other ports. A request-grant protocol is used to route packets from ingress to egress. When a packet is received, a request signal is issued. After the request reaches the egress side, a grant signal is generated based on some fixed threshold indicating there is space in the egress buffer to absorb the largest packet size dispatched from ingress. The buffer must be sized deep enough to accommodate in-flight traffic associated with a scenario where heavy congestion is found after the grant is issued. Awaiting a grant signal to arrive before dispatching packets incurs significant end-to-end latency. To alleviate this problem, a speculative packet dispatch approach (SPD) is proposed in which the request grant protocol is completely eliminated. Packets are dispatched speculatively from ingress to egress based on predictions that there is enough space in the egress buffer. This is achieved by incorporating an LSTM recurrent neural network as part of the VOQ controller. The LSTM is trained by time-series data sets generated from past observations on the queue occupancy. The experimental results show that SPD delivers excellent improvement on the system performance, reduces buffering requirements and preserves the property of VOQ.

Toward a High-Performance and Low-Loss Clos–Benes-Based Optical Network-on-Chip Architecture

As chip multiprocessors (CMPs) keep growing in capability, on-chip communication efficiency is crucial to the overall performance. However, on-chip networks based on electronic switches suffer from excessive power consumption and limited performance. In order to take advantages of optical interconnect, we propose an optimized design toward a high-performance and low-loss Clos–Benes-based hierarchical optical network-on-chip (NoC) for large-scale CMPs. We propose several key techniques, including a loss-aware adaptive (LAA) routing for intraswitch Benes network, a priority-based round-Robin virtual output queue selection and a $Q$ -learning-based heuristic routing for interswitch Clos network, and a local transfer link (LTL) technique to improve the traffic locality. A case study on a 256-core CMP under uniform traffic shows that the network throughput is increased by 346.7%, 61%, and 12.9%, respectively, than the mesh, fattree, and the traditional generic Clos–Benes optical NoC. On average of a set of real applications, the application end-to-end delay is reduced by 47.6%, 28.2%, and 19.4%, respectively, than the mesh, fattree, and the traditional generic Clos–Benes network. Meanwhile, the average optical power loss is decreased by 11.8% and 49.9%, respectively, as compared to the mesh and fattree. As compared to a baseline Clos–Benes network, the use of LAA routing together with the LTL could reduce the average optical power loss by 28.4%.

Randomized scheduling algorithm for virtual output queuing switch at the presence of non-uniform traffic

<span>Virtual Output Queuing (VOQ) is a well-known queuing discipline in data switch architecture that eliminates Head Of Line (HOL) blocking issue. In VOQ scheme, for each output port, a separate FIFO is maintained by each input port. Consequently, a scheduling algorithm is required to determine the order of service to virtual queues at each time slot. Maximum Weight Matching (MWM) is a well-known scheduling algorithm that achieves the entire throughput region. Despite of outstanding attainable throughput, high complexity of MWM makes it an impractical algorithm for implementation in high-speed switches. To overcome this challenge, a number of randomized algorithms have been proposed in the literature. But they commonly perform poorly when input traffic does not uniformly select output ports. In this paper, we propose two randomized algorithms that outperform the well-known formerly proposed solutions. We exploit a method to keep a parametric number of heavy edges from the last time matching and mix it by randomly generated matching to produce a new schedule. Simulation results confirm the superior performance of the proposed algorithms.</span>

Randomised scheduling algorithm for virtual output queuing switch at the presence of non‐uniform traffic

Virtual Output Queuing (VOQ) is a well-known queuing discipline in data switch architecture that eliminates Head of Line (HOL) blocking issue. In VOQ scheme, for each output port, a separate FIFO is maintained by each input port. Consequently, a scheduling algorithm is required to determine the order of service to virtual queues at each time slot. Maximum Weight Matching (MWM) is a well-known scheduling algorithm that achieves the entire throughput region. Despite of outstanding attainable throughput, high complexity of MWM makes it an impractical algorithm for implementation in high-speed switches. To overcome this challenge, a number of randomised algorithms have been proposed in the literature. They commonly perform poorly when input traffic does not uniformly select output ports. Here, the authors propose two randomised algorithms that outperform the well-known formerly proposed solutions. They exploit a method to keep a parametric number of heavy edges from the last time matching and mix it by randomly generated matching to produce a new schedule. Simulation results confirm the superior performance of the proposed algorithms.

Highest Rank First: A New Class of Single-Iteration Scheduling Algorithms for Input-Queued Switches

In this paper, we study a new class of single-iteration scheduling algorithms for input-queued switches based on a new arbitration idea called highest rank first (HRF). We first demonstrate the effectiveness of HRF by a simple algorithm named Basic-HRF. In Basic-HRF, virtual output queues (VOQs) at an input port are ranked according to their queue sizes. The rank of a VOQ, coded by $\log (N+1)$ bits, where $N$ is the switch size, is sent to the corresponding output as a request. Unlike all existing iterative algorithms, the winner is selected based on the ranks of the requests/grants. We show that the rank-based arbitration outperforms the widely adopted queue-based arbitration. To improve the performance under heavy load and maximize the match size, Basic-HRF is integrated with an embedded round-robin scheduler. The resulting HRF algorithm is shown to beat almost all existing single-iteration algorithms. But, the complexity of HRF is high due to the use of multi-bit requests. A novel request encoding/decoding mechanism is then designed to reduce the request size to a single bit while keeping the original performance of HRF. A unique feature of the resulting coded HRF (CHRF) algorithm is that the single-bit request indicates an increase or decrease of a VOQ rank, rather than an empty VOQ or not. We show that the CHRF is the most efficient single-bit-single-iteration algorithm.

New Scheduling Algorithms for Agile All-Photonic Networks

AbstractAn optical overlaid star network is a class of agile all-photonic networks that consists of one or more core node(s) at the center of the star network and a number of edge nodes around the core node. In this architecture, a core node may use a scheduling algorithm for transmission of traffic through the network. A core node is responsible for scheduling optical packets that arrive from edge nodes and switching them toward their destinations. Nowadays, most edge nodes use virtual output queue (VOQ) architecture for buffering client packets to achieve high throughput. This paper presents two efficient scheduling algorithms called discretionary iterative matching (DIM) and adaptive DIM. These schedulers find maximum matching in a small number of iterations and provide high throughput and incur low delay. The number of arbiters in these schedulers and the number of messages exchanged between inputs and outputs of a core node are reduced. We show that DIM and adaptive DIM can provide better performance in comparison with iterative round-robin matching with SLIP (iSLIP). SLIP means the act of sliding for a short distance to select one of the requested connections based on the scheduling algorithm.

An improved communication scheme for non-HOL-blocking wireless NoC

As the wireless interface often requires handling numbers of data simultaneously in wireless network-on-chip, it potentially causes data congestions. The degradation of wireless data transfer can tremendously reduce the efficiency of the network communication. In this paper, virtual output queuing (VOQ) technique has been used to eliminate the head-of-line blocking issue. Moreover, a novel and effective communication scheme has also been introduced to alleviate the traffic load in wireless nodes and hence improving the efficiency of wireless communication. Simulation results indicate that our proposed architecture is advantageous in various aspects including the transfer latency, network throughput and energy consumption.

On Iterative Scheduling for Input-Queued Switches With a Speedup of $2-1/N$

An efficient iterative scheduling algorithm for input-queued switches, called round robin with longest queue first (RR/LQF), is proposed in this paper. RR/LQF consists of three phases: report, grant, and accept. In each phase, only a single-bit message per port is sent for reporting a packet arrival, granting an input for packet sending, or accepting a grant. In both the grant and accept phases, scheduling priority is given to the preferred input–output pairs first and the longest virtual output queuing (VOQ) next. The notion of the preferred input–output pair is to keep a global RR schedule among all the inputs and the outputs. By serving the preferred input–output pairs first, the match size tends to be maximized. By serving the longest VOQ next, the match weight is also boosted. When RR/LQF is executed for a single iteration (i.e., RR/LQF-1), we show by simulations that RR/LQF-1 outperforms all the existing single-bit-single-iteration scheduling algorithms. When RR/LQF is executed up to $N$ iterations (i.e., RR/LQF- $N$ ), we prove that under any admissible traffic pattern, RR/LQF- $N$ is stable with a speedup of $2-1/N$ , where $N$ is the switch size. To the best of our knowledge, this is the first work showing that an iterative scheduling algorithm is stable with a speedup less than 2. We then generalize RR/LQF to become a class of algorithms that have the same speedup bound of $2-1/N$ . Efforts are then made to further reduce the implementation complexity of RR/LQF. To this end, the pipelined RR/LQF and RR/RR, a simpler variant of RR/LQF, are proposed.

Contentionless Architecture for Optical Interconnect (CAOI) in Data Center Network

Emerging web-based and cloud computing applications are creating the need for powerful data center networks (DCN). Optical interconnects are replacing their electrical counterparts due to their benefits. An optical interconnect that eliminates contention is proposed, hereafter called CAOI. It eliminates electronic buffering and virtual output queues which reduces the latency. Fixed data rate is guaranteed under any traffic pattern. A large class of DCN applications can be supported by this architecture. Benefits of optical wavelength division multiplexing, optical code division multiple access and optical space division multiplexing are exploited. All-to-one communication is worst communication pattern encountered in any DCN application. The performance of the proposed architecture is compared for many-to-many and all-to-one communication pattern.

Formula omitted]-WiNoC: Exploring scalable wireless on-chip micronetworks for heterogeneous embedded many-core SoCs

Modern embedded SoC design uses a rapidly increasing number of processing units for ubiquitous computing, forming the so-called embedded many-core SoCs (McSoC). Such McSoC devices allow superior performance gains while side-stepping the power and heat dissipation limitations of clock frequency scaling. The main advantage lies in the exploitation of parallelism, distributively and massively. Consequently, the on-chip communication fabric becomes the performance determinant. To bridge the widening gap between computation requirements and communication efficiency faced by gigascale McSoCs in the upcoming billion-transistor era, a new on-chip communication system, dubbed Wireless Network-on-Chip (WiNoC), has been proposed by using the recently developed RF interconnect technology. With the high data-rate, low power and ultra-short range interconnection provided by UWB technology, the WiNoC design paradigm calls for effective solutions to overhaul the on-chip communication infrastructure of gigascale McSoCs.In this work, an irregular and reconfigurable WiNoC platform is proposed to tackle ever increasing complexity, density and heterogeneity challenges. A flexible RF infrastructure is established where RF nodes are properly distributed and IP cores are clustered. Consequently, a performance-cost effective topology is formed. A region-aided routing scheme is further deigned and implemented to realize loop-free, minimum path cost and high scalability for irregular WiNoC infrastructure. To implement the data transmission protocol, the RF microarchitecture of WiNoC is developed where the RF nodes are designed to fulfill the functions of distributed table routing, multi-channel arbitration, virtual output queuing, and distributed flow control. Our simulation studies based on synthetic traffics demonstrate the network efficiency and scalability of WiNoC.

A COMBINED LOW LATENCY AND WEIGHTED FAIR QUEUING BASED SCHEDULING OF AN INPUT-QUEUED SWITCH

Input queuing has become dominant and popular building blocks for high speed crossbar switches with many ports and fast line rates because they require minimum speed-up of memory bandwidth. Input Queued switches with finite Virtual Output Queues guarantees QoS performance in terms of throughput and average delay. A switch performs two functions Queuing and Scheduling. Queue Management algorithm manages the size of the queues and drops packets when necessary or appropriate. Scheduling algorithms determine next packet to transfer and solves conflicts with the switching fabric. Fairness and Starvation are another two properties of IQ switches and it is analyzed in finite VOQ in this works. Fairness performs fair allocation of bandwidth among flows and prevents flows from misbehaving flows. Starvation of VOQ prevents serving High priority queue. The motivation behind this study is to schedule the HoL packets queued in finite VOQs by Framing with Low Latency Queuing (LLQ) and Weighted Fair Queueing (WFQ). This queueing technique of VOQ is measured in terms of throughput and average delay by fair allocation of bandwidth with WFQ and Starvation-free queue with LLQ.

On the Design, Implementation, Analysis, and Prototyping of a 1- μs, Energy-Efficient, Carrier-Class Optical-Ethernet Switch Router

The integration of layer-2 carrier-class packet technologies with optical transport network is termed as packet-optical integration and is being deployed by service providers for migration from legacy SONET/SDH systems. We present a state-of-the-art carrier-class switch router that facilitates packet-optical integration, thereby achieving best of both the optical and packet worlds. The premise of this switch router is the use of carrier ethernet technology as a packet enabler for achieving statistical multiplexing at fine granularities, while maintaining rich operations, administration, maintenance, and provisioning features. To this end, we proposed the omnipresent ethernet concept that uses binary routing and source routing to support: 1) layer 2 and layer 3 switching and routing, 2) low latency of the order of 1–5 μs even for layer 3 processing, and 3) low-energy consumption. The omnipresent ethernet framework leads to a software defined networking solution, whereby a centralized controller admits services and configures nodes based on homogenous networking parameters. In this paper, we report a commercial implementation of a packet-optical network demonstrated by our designed, fabricated, developed carrier ethernet switch router (CESR). We discuss the architectural considerations, design, and implementation of both the hardware and the control software. A switch architecture achieving 1-μs port-to-port delay across layers 1, 2, and 2.5 based on an opportunistic principle of virtual output queuing is showcased. The novelty is a scalable 96-Gbps cross connect fabric implemented in a field programmable gate array using a two-stage buffer system. A multistate software defined control plane is also reported. An exact analysis of the switch architecture using a combinatorial G/G/1 model is developed. An energy audit of the CESR is showcased. A test bed in the lab replicating a field deployment is presented. An exhaustive set of test cases are developed to test our designed CESR. Results are shown for latency, throughput, service support, frame-size stability, power, and bit error rate, thus validating our design.

Fair Chance Round Robin Arbiter

With the advancement of Network-on-chip (NoC), fast and fair arbiter as the basic building block for high speed switches/routers gained attention in recent years. In this paper I propose the fair chance round robin arbiter (FCRRA), a high speed, low power and area efficient RRA for NoC applications. The FCRRAG tool propose in this paper can generate a design for bus arbiter, which can handle the exact number of bus masters for both on chip and off chip buses within one short cycle. General Terms i. Arbiters are electronic devices that allocate access to shared resources. ii. Virtual Output Queues (VOQs) [4]: there are VOQs in a switch to remove possible output port contention (Head of Line (HOL) blocking). iii. Bus Arbiter resolves bus conflicts when multiple bus masters request a bus in the same cycle.[4]

A Priority based SRM Algorithm for VOQ Packet Switch Architecture

Virtual Output Queuing (VOQ) is used to overcome the head-ofline (HoL) blocking problem in input-queued (IQ) packet switches. There are a lot of research has been devoted to design iterative arbitration algorithms to find maximum throughput of this architecture. In this paper approximating maximum size matching (MSM) algorithm called Selective Request Matching (SRM) has been proposed, which performs extremely well under various traffic models and easy to implement in hardware.

A Performance Evaluation of Multiple Input Queued (MIQ) Switch with Iterative Weighted Slip Algorithm

Many researchers had evaluated the throughput and delay performance of virtual output queued (VOQ) packet switches using iterative weighted/un-weighted scheduling algorithms. Prof. Nick Mckeown from Stanford University had evolved with excellent iterative maximal matching (i-slip) scheme which provides throughput near to 100%. Prof. Kim had suggested multiple input queued architecture which also provide more than 90 % throughput for less number of input queues per port. (In VOQ N queues per port are used). Our attempt is to use MIQ architecture and evaluate delay, throughput performance with i-slip algorithm for scheduling. While evaluating performance we had used Bernoulli’s and Bursty (ON-OFF) traffic models.