Abstract

Virtual Output Queuing (VOQ) is an architecture widely employed in modern networking products. Traffic from every ingress port is stored in a set of queues mirroring the structure of the egress ports. This architecture allows congestion on one egress port to be isolated from the other ports. A request-grant protocol is used to route packets from ingress to egress. When a packet is received, a request signal is issued. After the request reaches the egress side, a grant signal is generated based on some fixed threshold indicating there is space in the egress buffer to absorb the largest packet size dispatched from ingress. The buffer must be sized deep enough to accommodate in-flight traffic associated with a scenario where heavy congestion is found after the grant is issued. Awaiting a grant signal to arrive before dispatching packets incurs significant end-to-end latency. To alleviate this problem, a speculative packet dispatch approach (SPD) is proposed in which the request grant protocol is completely eliminated. Packets are dispatched speculatively from ingress to egress based on predictions that there is enough space in the egress buffer. This is achieved by incorporating an LSTM recurrent neural network as part of the VOQ controller. The LSTM is trained by time-series data sets generated from past observations on the queue occupancy. The experimental results show that SPD delivers excellent improvement on the system performance, reduces buffering requirements and preserves the property of VOQ.

Highlights

  • Higher demands on network switches and routers continue to increase since the early days of the Internet

  • This paper suggests a way to overcome these limitations by proposing a method called Speculative Packet Dispatch (SPD) where packets are speculatively dispatched from a Virtual Output Queuing (VOQ) on the ingress side

  • Simulations were performed using TensorFlow running on Google Colab for the Long Short Term Memory (LSTM)-based egress buffer occupancy prediction and using System Verilog simulated with Mentor Graphics ModelSim Verilog Simulator for the VOQ model

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Summary

Introduction

If a downstream device asserts a flow control signal to an egress port, congestion is created because the ingress rate is larger than the egress rate In both cases, packets need to be temporarily stored in the ingress or egress queues. A simple ingress-egress queueing structure has an inherent problem known as Head-of-Line (HOL) blocking, in which congestion in one egress port can cause considerable throughput degradation in other egress ports [10, 11] To solve this problem, an architecture known as Virtual Output Queuing (VOQ) was developed [5, 6]. The rest of this paper is organized as follows: sections 2 and 3 describe the VOQ and Time-Series LSTM, respectively, section 4 presents the proposed technique, section 5 discusses the experimental results and section 6 ends the paper with some concluding remarks

Virtual Output Queuing
Long Short Term Memory for Time Series Predictions
Experimental Results and Analysis
Egress Buffer Occupancy Prediction
Request Grant Delay
VOQ Performance
Minimum Egress Buffer Size Requirements
Conclusion and Future Work
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