Abstract
The high-performance computing paradigm needs high-speed switching fabrics to meet the heavy traffic generated by their applications. These switching fabrics are efficiently driven by the deployed scheduling algorithms. In this paper, we proposed two scheduling algorithms for input queued switches whose operations are based on ranking procedures. At first, we proposed a Simple 2-Bit (S2B) scheme which uses binary ranking procedure and queue size for scheduling the packets. Here, the Virtual Output Queue (VOQ) set with maximum number of empty queues receives higher rank than other VOQ’s. Through simulation, we showed S2B has better throughput performance than Highest Ranking First (HRF) arbitration under uniform, and non-uniform traffic patterns. To further improve the throughput-delay performance, an Enhanced 2-Bit (E2B) approach is proposed. This approach adopts an integer representation for rank, which is the number of empty queues in a VOQ set. The simulation result shows E2B outperforms S2B and HRF scheduling algorithms with maximum throughput-delay performance. Furthermore, the algorithms are simulated under hotspot traffic and E2B proves to be more efficient.
Highlights
In recent years, a lot of the commercial and scientific application requires high-performance computing (HPC)
We investigate the throughput performance of Highest Ranking First (HRF), Simple 2-Bit (S2B), and Enhanced 2-Bit (E2B) scheduling schemes under uniform traffic distribution
The effect of prioritizing the empty Virtual Output Queue (VOQ) during the scheduling process provides a considerable impact on S2B throughput performance, which manages a 5% improvement than HRF at all load levels
Summary
A lot of the commercial and scientific application requires high-performance computing (HPC). Among all the types of crossbars, input queued switch remains simple to implement and more effective because the memory bandwidth required for packet transmission at each timeslot is very less This makes it highly preferred and most suitable for high-speed communications in Internet routers or data centers [7,8,9]. Completing all the iterations and making scheduling decisions within the minimum duration of 5 ns is a highly challenging task This time-critical task offer severe headache to scheduling schemes used in high-speed switches. The severity of task might lead to additional timeslot or in need of speedup This will further reduce the switch performance or increase the implementation complexity, for the latter case. A high-performance scheduling algorithm is required to attain maximum matching at every timeslot to meet the demand of compute-intensive applications.
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