Virtual Junction Research Articles

Reliability of SiC MOSFETs in the High Cycle Fatigue Regime under Fast Power Pulses

Device reliability is an important factor in application, especially in the field of electric mobility. In this paper high cycle fatigue power cycling results of SiC devices in baseplate free modules are presented. To minimize testing time, the devices were stressed with load pulses corresponding to a 50 Hz load. The reliability results are the first fatigue results for temperature swings below 30 K for SiC devices. The lifetime in the high cycle fatigue area is limited by solder fatigue for high virtual junction temperatures of 150 °C. In theory, the reliability should increase exponential since the elastic-plastic transition area is reached. The experiment revealed that the lifetime can still be described by the Coffin-Manson approach also in the high cycle fatigue area. It can be observed that the high junction temperatures weaken the stability of the solder layer, so no major lifetime increase can develop. The measured temperature data are additionally corrected by a three-dimensional (3D) simulation to ensure a validity of the results.

Thermal Design of Stacked Power Modules for Electric Drive Applications

This paper reports the thermal design of a stacked arrangement inserting four IGBT modules between five heat sinks to achieve good cooling performance while enabling them to be installed into the limited space. Such stacked four IGBT modules can be used for a variable voltage converter (VVC), a three-phase motor inverter (M-INV) and a three-phase generator inverter (G-INV) of one electric control system in one electric vehicle or hybrid electric vehicle. Work presented in this paper are the thermally related structure design and thermalelectric and computational fluid dynamics coupled simulation, while the prototyping and thermal test of the stacked arrangement are still ongoing. The simulation results indicate that the stacked arrangement can be designed into a compact 121 mm × 94.7 mm × 90.8 mm structure while achieving the maximum virtual junction temperature below 150°C under the coolant feed temperature of 70°C, flow rate of 10 L/min and pressure drop of 0.16 bar for the VVC delivering 150 kW, the M-INV delivering 100 kW and the G-INV delivering 50 kW. If validated with the ongoing work, the stacked arrangement can be employed to increase power density and improve electrical and thermal performance of the power modules in the electric control systems with multiple converters/inverters.

Measurement Deviation of the Virtual Junction Temperature by the Saturation Voltage Drop Method for Insulated-Gate Bipolar Transistors

Measurement Deviation of the Virtual Junction Temperature by the Saturation Voltage Drop Method for Insulated-Gate Bipolar Transistors

Real-Time Average Junction Temperature Estimation for Multichip IGBT Modules With Low Computational Cost

The junction temperature of the insulated gate bipolar transistor (IGBT) modules is a vital parameter for the reliability of the power electronic system. For effective thermal management, it is necessary to estimate junction temperature in real time. However, existing thermal models have limitations to achieve fast temperature prediction for multichip IGBT modules. In this study, we investigate the real-time junction temperature prediction for multichip IGBT modules with low computational cost. According to the power module' structure, an average 2D thermal model with physical significance is proposed to predict the virtual junction temperature for multichip IGBT modules, which can be extracted from finite element model based on the least square method. To further improve the computational efficiency, a temperature predictor based on the staggered cycle-by-cycle calculation method is proposed and its prediction error under various extreme operation conditions is analyzed by enumeration method. Finally, the comprehensive experimental results verify the effectiveness of the proposed average thermal model and junction temperature prediction method.

Monitoring Initial Solder Layer Degradation in a Multichip IGBT Module via Combined TSEPs

With the development of high power converters, the safe operation of large IGBT modules with parallel chips is of increasing importance. In a multichip module, uneven solder layer degradation translates into higher thermal resistance for some of the chips, leading to junction temperature differences between them. However, the specific meaning of a virtual junction temperature extracted from any external electric characteristic parameter of the module is not yet clear. This paper studies the physical meanings of the temperatures estimated by the threshold voltage and the Miller platform duration as well as the quasi turn- off delay time. Experimental results show that the temperature estimated from the threshold voltage is close to the highest temperature of all the chips, while that estimated from the Miller platform duration or quasi turn-off delay time is close to the average chip temperature. Making use of the difference between the two, this paper proposes a new method to monitor the initial solder layer degradation in the multichip IGBT module. Such a method using combined temperature sensitive electric parameters (TSEPs) is verified for different levels of degradation.

Analysing Efficiency and Reliability of High Speed Drive Inverters Using Wide Band Gap Power Devices

Within the project ‘ARIEL’ an electrical turbo compressor unit for fuel cell applications is deeply investigated. The necessary drive inverter is especially designed for high fundamental frequency and high switching frequency to cope with the requirements of the implemented electrical machine. This paper presents investigations on the inverter’s efficiency and its prospective lifetime at different stages of the development. In the design process different wide band gap power semiconductor devices in discrete packages are evaluated in terms of the achievable power density and efficiency, both by simulations and measurements. Finally, an optimised design using surface mount silicon carbide MOSFETs is developed. Compared to a former inverter design using silicon devices in a three-level topology, the power density of the inverter is significantly increased. The lifetime of power electronic systems is often limited by the lifetime of the power semiconductor devices. Based on loss calculations and the resulting temperature swing of the virtual junction the lifetime of the inverter is estimated for the most frequent operating points and for different mission profiles.

Investigation on the accuracy of the junction temperature determined by the VCE(T) method under different load pulse durations in power cycling test

There is an argument that the VCE(T) method is not a sufficient junction temperature measurement method in the power cycling test (PCT) under the short load pulse duration. In this paper, the influence of load pulse duration on the junction temperature measurement in PCT is investigated through numerical simulation and verification experiment, especially the comparison of two commonly used junction temperature definitions: chip surface average temperature Tavg measured by the infrared camera and virtual junction temperature Tvj measured by the VCE(T) method. To this end, an improved simulation method to calculate the Tvj and a special methodology to the Tavg evaluation are proposed for fair comparison in this work. Finally, the root cause of deviation between two junction temperature definitions is discussed and the numerical relationship between the deviation and temperature gradient and average surface temperature is given based on a large number of simulation results. The results show that different load pulse durations essentially change the temperature gradient and average temperature of the chip surface, as long as the chip temperature is not uniform, the Tvj is always higher than the Tavg, and the deviation mainly depends on the temperature gradient, which shows a power law in a wide range.

The Influence and Application of Bond Wires Failure on Electrothermal Characteristics of IGBT Module

The bond wires failure is one of the most common failure modes of the insulated gate bipolar transistor (IGBT) module, which will cause an increase in the overall ON-state voltage drop V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> , and it is generally believed to not affect the junction-to-case thermal resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">thjc</sub> . The measured V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> mainly consists of two parts: the voltage drop of the IGBT chip V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE_Chip</sub> and that of the bond wire V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE_wire</sub> ; the influence of bond wires failure on V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> should be discussed and explained in two parts. However, these actual measurement parameters are not considered before. In this article, the impact mechanism of bond wires failure on electrothermal characteristics of the IGBT module is analyzed with the help of realistic simulation models and experiment verification. The results show that the bond wires failure only affects V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE_wire</sub> , and the impact on V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE_Chip</sub> is small, which can be ignored. Meanwhile, the increase in the virtual junction temperature is not caused by the increase in the power loss of the IGBT chip but by the increase in the current density of bond feet, which is caused by the decrease in the effective contact area. Besides, the measured R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">thjc</sub> is not the intrinsic thermal resistance but slightly smaller than the intrinsic thermal resistance, and it decreases as the bond wires failure. Furthermore, the proposed mechanism can provide method guidance for the separation strategy of concurrent failure modes of IGBT modules only by monitoring the ON-state voltage drop.

Assessment of Catastrophic Failure for Phase Control Thyristors in AC Pulsed Applications

This article presents a theoretical development, supported by experimental results, which is useful for the evaluation of the ride through capability of phase control thyristors that should operate under high multicycle ac, power frequency current surges with different amplitudes between cycles. Despite being commonly found in the field of metals industry applications, this is not a standard data sheet test condition that can be readily used to predict if the device can handle a given surge profile. The present work is devoted to contributing to the fulfillment of this gap. A recursive, discrete-time method is used for the calculation of instantaneous virtual junction temperature of the devices tested. Such method is advantageous over the traditional equivalent power pulse technique since for any given time step only the immediately previous calculation is needed instead of the overall series. It is shown that the results obtained with these two methods are practically identical. Besides, a complete study based on a commercial power semiconductor device is given along with experimental results that support the application of the assessment method developed.

Theoretical study on optimization criterion of the triple RESURF lateral power devices via virtual junction concept

The triple reduced surface field (T-RESURF) technique allows the drift region to achieve a much higher doping concentration while maintaining its breakdown voltage unaffected. Yet, as a result of the missing design guidance, the optimization of the T-RESURF effect is difficult to be realized in practice. In light of that, in this paper, the Virtual Junction Concept is proposed to provide the optimization criterion and explore physical insight of the T-RESURF effect. The proposed method bypasses the complicated 2D analysis by equivalenting the 2D drift region to a 1D virtual junction. The effectiveness and correctness of such a method are validated by the good agreement between modeled and simulated results. Benefit from its simplicity and veracity, the proposed method can not only conduct qualitative and quantitative analysis on the T-RESURF effect but also capable of providing design guidance and optimization criterion.

The logical perception of the pure consciousness

Does pure consciousness exist without being hooked to a physical mechanism (e.g. human body)? Can such claim be proven logically? The magnitude of asking this sort of question is similar to asking: Is it logical that matter exists out of the total void? The answer to both questions is yes. The aim of this paper is to show that, the existence of pure consciousness is a logical state, it is not energy, and it exists timelessly and can be experienced beyond the physical body. Furthermore, we show that pure consciousness (the soul) is a virtual junction on the metaphysical virtual net where each junction incorporates a set of cords of consciousness. The set can be limited, unlimited or uncountable. Cords of consciousness is treated as brain neural patterns and as such the brain can easily be manipulated by an external device which may transmit neural patterns in order to generate artificial scenes. A computation example was provided to elaborate the neural patterns and cords of consciousness. Finally, we discuss the opportunity rather than the possibility to visit the metaphysical virtual space. In that sense, if it is possible, should we grab the opportunity and expend our science beyond physics, into the metaphysics?

An 800-V High-Density Traction Inverter—Electro-Thermal Characterization and Low-Inductance PCB Bussing Design

The need to increase the power density of traction inverters for the electrified transportation systems offers an opportunity to adopt silicon carbide (SiC) devices. To ensure the system reliability, it is critical to select a SiC power module that can dissipate a sufficient amount of power to avoid operating beyond the maximum allowed junction temperature. In this work, a comprehensive electro-thermal characterization procedure based on the virtual junction temperature concept is proposed to characterize the module’s maximum power dissipation as a function of coolant temperature. Using the characterization results, it is feasible to determine the module’s safe operating area for a traction application in terms of the switching frequency and the coolant temperature. The proposed characterization method is demonstrated on a custom 1200-V SiC module to validate its feasibility for an 800-V, 150-kVA traction inverter system. In addition, the design approach for a low-inductance bussing structure using heavy copper printed circuit board (PCB) is presented in this work, which leads to a snubberless, compact and low-cost system design. Measurements and experimental studies have been performed to validate the effectiveness of PCB bussing design. The overall volume of the inverter system is around 1.75 L, which leads to a volumetric power density of 86 kVA/L.

Temperature Distribution Evaluation of Single Chip by Multiple Currents V CE (T) Method

With the ever-growing power density in power electronics, the temperature difference between the center and the edge of a chip can easily exceed 40 K, which poses a serious challenge to the reliability of power devices, and evaluation of single-chip temperature distribution will be more significant than classical virtual junction temperature for reliability assessment. In this article, a multicurrent V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> ( T) method is proposed to evaluate the single-chip temperature distribution. Unlike the conventional V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> ( T) method measuring the saturation voltage at only one small measurement current, this method requires that the voltages are measured at multiple different measurement currents, and then, the temperature distribution is obtained by solving a system of nonlinear equations. To improve the accuracy of the solution, the chip temperature distribution is represented by a mathematical function, which can greatly reduce the unknown parameters in the equations. Two common different shapes (square and rectangle) of the chip are chosen as research objects, this method is successfully applied in the dc power cycling test and verified by the infrared (IR) camera, and the calculation results agreed well with experimental results. Moreover, the possible effects of the introduction of mathematical models on the evaluation results have been discussed. The proposed method extends the conventional V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> ( T) method and finds its capability in chip temperature distribution evaluation, which could help investigate fatigue failure from different perspectives.

Effects of solder degradation on the die temperature measurement via internal gate resistance

The virtual junction temperature measurement via internal gate resistance (Tvg) is attractive for the health monitoring of power modules. Using the gate resistance as Temperature Sensitive Electrical parameter (TSEP) permits precise and timely absolute temperature on the die where the gate is located. This paper investigates how this measurement relates to other parts of the power die, inclusive of aging effects such as die attach degradation. Using in-situ measurements and FEM simulations, a method for compensating the gate pad temperature error is proposed.

Impact of the sensing current density on PN-junction based temperature estimation methods for Si and SiC power devices

In this work, the impact of the sensing current density on the virtual junction temperature estimation methods for Si IGBTs and SiC MOSFETs using the pn junction voltage drop as TSEP was investigated. For this purpose, measurements of the temperature characteristics at different sensing current densities were performed on several Si and SiC devices. Additionally, TCAD simulations were performed to verify the measurement results. So far, 0.1% of the devices nominal current is commonly accepted as sensing current guideline for Si IGBTs and with the results of this investigation, this guideline was verified and examined regarding their applicability for SiC MOSFETs. The results indicate that whereas 0.1% of the devices nominal current yield an applicable sensing current for Si IGBTs, this guideline does not deliver a suitable sensing current for the tested SiC MOSFETs. As a consequence, a different approach to determine a suitable sensing current for SiC MOSFETs is proposed.

Thermal Characterization of Silicon Carbide MOSFET Module Suitable for High-Temperature Computationally Efficient Thermal-Profile Prediction

This article characterizes the thermal behavior of a commercialized silicon carbide (SiC) power MOSFET module with special concerns on high-temperature operating conditions as well as particular focuses on SiC MOSFET dies. A temperature-dependent Cauer-type thermal model of the SiC MOSFET is proposed and extracted based on offline finite-element simulations. This Cauer model is able to reveal the temperature-dependent thermal property of each packaging layer, and it is suitable for the high-temperature thermal-profile prediction with sufficient computational efficiency. Due to the temperature-dependent thermal properties of the SiC die and ceramic material, the junction-heatsink thermal resistance can be increased by more than 10% under high-temperature conditions (up to 200 °C), which can considerably worsen thermal estimations of the SiC die and its packaging materials. Furthermore, the experimental measurement of transient thermal impedance was conducted under operating temperature variations (with virtual junction temperature ranging from 60.5 °C to 199.6 °C), and the effectiveness of the proposed temperature-dependent Cauer model was fully validated.

Investigations on Averaging Mechanisms of Virtual Junction Temperature Determined by V CE (T) Method for IGBTs

In this article, the physical meaning of the virtual junction temperature determined by the ${V}_{\text {CE}}$ ( ${T}$ ) method for insulated gate bipolar transistors (IGBTs), especially the averaging mechanisms, have been studied in depth to answer the question of which physically meaningful value of the chip is associated with the virtual junction temperature. A combination of theoretical analysis and electro-thermal simulation is performed to discuss the influence of temperature gradient on the virtual junction temperature, including vertical and lateral gradient. Furthermore, the averaging mechanisms of the virtual junction temperature are investigated and verified by effective experimental results. The results show that the virtual junction temperature is not a fixed value but a value related to the measurement current and is neither the area-weighted average temperature NOR the current-weighted average temperature, but it is in between. It provides guidance for understanding the virtual junction temperature in the measurement and defining the virtual junction temperature in the finite element model (FEM) simulation.

Gated Schottky Diode-Type Synaptic Device with a Field-Plate Structure to Reduce the Forward Current.

A gated Schottky diode with a field-plate structure is proposed and investigated as a new low-power synaptic device to suppress the forward current of the Schottky diode. In a hardware-based neural network, unwanted forward current can flow through gated Schottky diode-type synaptic devices during integration operations, possibly causing a malfunction of the neural network and increasing the power consumption. By adopting a field-plate structure, a virtual pn junction to suppress the forward current of the Schottky diode is formed in the poly-Si active layer. As a result, the unwanted forward current of the gated Schottky diode is successfully reduced to less than 1 pA/µm.

Online IGBT Temperature Measurement via Leakage Current in HTRB Test

To evaluate the reliability of endure high voltage when IGBT is turned off and eliminate the defective devices, HTRB (High Temperature Reverse Bias) test is one of the necessary tests for IGBT before it’s produced. According to the IEC standard, DUTs (Device Under Test) are usually blocked, and bear forward bias voltage, which is preferably 80% of VCESmax. During the HTRB test, DUT junction temperature should be set at maximum virtual junction temperature Tvj(max) which is usually between 125°C to 150°C. Due to high voltage, even though the leakage current is very low, high-power semiconductor devices generate dissipated power during HTRB test, which lead to junction temperature increase. And to access the reliability accurately, the rise of temperature cannot be neglected. To insure the test is carry out at standard temperature, this paper monitors DUTs junction temperature by using leakage current as a TSEP (Temperature Sensitive Electrical Parameter),. The experiment proofs that higher the junction temperature is, the more accurate the measure results will be, in the operating temperature range. In this paper, thermal resistance measurement is used to evaluate the validity of this method.

Center of mass and junction based data routing method to increase the QoS in VANET

In this paper, we have minimized the problems for Vehicle to Vehicle communication, caused by the speed of the cars, the obstruction caused by high rise buildings and routing loop problem at the road junction. This causes less throughput and data packet drops for a given network. In order to avoid these problems, we have defined a set of fixed junction points (FJP), any particular vehicles around FJP, is assigned as a transceiver for the data communication. That vehicle, called Virtual junction point (VJP) which has assigned weight to every road, depends on number of cars on that road and the distance between two junctions points along that road. Apart from the concept of VJP, a newly developed method, we call it Center of Mass (CM) method, is used by source vehicle for selecting the next forwarding vehicle. In this method, one minimizes the sum of all the distances of all neighboring vehicles from a given imaginary point, which is the CM point. In this point, physically there may not be any vehicle, but the vehicle close to that point is used for the next forwarding vehicle in our method. Simulation result shows our method performs better than other protocols.