Monitoring Initial Solder Layer Degradation in a Multichip IGBT Module via Combined TSEPs

Abstract

With the development of high power converters, the safe operation of large IGBT modules with parallel chips is of increasing importance. In a multichip module, uneven solder layer degradation translates into higher thermal resistance for some of the chips, leading to junction temperature differences between them. However, the specific meaning of a virtual junction temperature extracted from any external electric characteristic parameter of the module is not yet clear. This paper studies the physical meanings of the temperatures estimated by the threshold voltage and the Miller platform duration as well as the quasi turn- off delay time. Experimental results show that the temperature estimated from the threshold voltage is close to the highest temperature of all the chips, while that estimated from the Miller platform duration or quasi turn-off delay time is close to the average chip temperature. Making use of the difference between the two, this paper proposes a new method to monitor the initial solder layer degradation in the multichip IGBT module. Such a method using combined temperature sensitive electric parameters (TSEPs) is verified for different levels of degradation.