Virtual Circuit Research Articles

Adaptive On-Time Control Buck Converter with a Novel Virtual Inductor Current Circuit

This study presents a new virtual inductor current circuit to reduce circuit complexity, which is not necessary to sense inductance current directly. The buck converter was designed to produce an output voltage of 1.0–2.5 V for a 3.0–3.6 V input voltage. The load current range was from 100 mA to 500 mA. It was simulated and verified by SIMPLIS and MathCAD. The simulation results of this buck converter show that the voltage error is within 1%, and the recovery time is smaller than 2 ms for step-up and step-down load transients. Additionally, it achieves less than 26 mV overshoot at full-load step transient response. The circuit topology would be able to fabricate using TSMC 0.35 mm 2P4M CMOS technology. The control mechanism, implementation, and design procedure are presented in this paper.

Teaching IC Timer through simulation for future STEM teacher

Teaching in the STEM field based on the simulation is the necessary for students to understand the concepts and materials that have been given. This paper presents a simulation performed using IC Timer to generate a square signal using a virtual laboratory circuit wizard simulation software. In conducting the simulation, there are stages that will be given to students. There are 10 stages that will be explained in the lab experiments section. The method used consists of design for simulation. With this paper, it is expected that future teachers can provide simulated teaching to their students well. The results obtained in the simulation using this IC Timer are square signals that can be generated by the IC Timer circuit, and the results of frequency calculations, both through theoretical calculations and calculations with an oscilloscope do not show significant results. Teachers can provide teaching to students through simulation with a virtual laboratory first before carrying out practice directly, so students can use real devices properly and can reduce the risk of damage.

Design of Network on Chip (NoC) Computing Node for Mesh Topology using Soft-core NIOS-II Processor

Paper discusses the design of computing node for Mesh topology-based Network on Chip (NoC) platform. The computing node has a capability of processing and routing data over four I/O port switch. Mesh topology is popular due to scalability and its simplest form. The platform is design for (N x N) computing nodes, where each node has soft-core based ‘NIOS-II’ processor. Each computing node has four-way switch East, West, North, South and one local port. The Mesh topology uses static look-up table optimized using proper routing algorithms. The lookup table information is used by Virtual Circuit Interface (VCI) of the switch node to forward the packets using combination of priority based round robin diagonal propagation scheduling algorithm. The design of computing node is generated using – Quartus-II ALTERA software and simulated for functional simulation. Such platforms are popular for data parallelism having applications in Smart sensors.

Research and implementation of virtual circuit test tool for smart substations

Abstract This paper describes the technologies of virtual circuit and analyzes the SCL configuration files of smart substation. Based on the traditional virtual circuit test method, the visual technique of .NET is employed to develop the smart substation virtual circuit test tool accorded with the standard of IEC61850 9-2, the static test scheme and dynamic test scheme are presented respectively. The problem of SCL configuration of smart substation network could be detected quickly by the visual simulation of secondary virtual circuit for smart substation. Our work provides an effective virtual circuit test tool for smart substations.

Design and implementation of electronic circuit virtual laboratory based on virtual reality technology

Virtual reality technology has been applied in virtual labs and remote experiment teaching. This paper designs an electronic circuit virtual laboratory based on virtual reality technology, and relevant experimental teaching content. The system uses Unity 3D and 3ds max tools to build a three-dimensional model of general instrumentation, electronic components, and laboratory scenes in electronic circuit experiments. The C# is used to develop general virtual instrumentation functions and electronic circuit simulation, the electronic circuit virtual reality laboratory based on VR equipment was realized. We have developed VR electronic circuit virtual laboratory on PC and web. Students can use VR electronic circuit virtual laboratory to learn basic electronic circuit knowledge and carry out electronic circuit virtual experiment immersively.

VCS: A method of in-order packet delivery for adaptive NoC routing

Adaptive routing proves its efficiency in sustaining higher network performance bypassing packets through alternate congestion-free minimal or non-minimal routes for a many-core on-chip communication system. It prevents the network from reaching an early saturation due to the stalling of packets in the priority-fixed shortest route for a longer period. However, routing packets adaptively to an alternate route instead of choosing the priority-fixed and shortest route may lead to an unintended state of delivering packets out-of-order sequence at the destination node that is not accepted by many message-passing systems. This ordering mismatch is due to allowing multiple alternate routes for packets of the same communication flow in adaptive mode. In such a case, a packet with a higher sequence number takes over another packet of the same communication flow having a lower sequence number. Storing and reordering all unordered packets of the same communication flow at the sink side becomes costlier due to the increasing area and power requirement. Ideally, the added memory size reaches to infinity for storing all unordered packets that belong to the same communication flow. In the proposed method, we guarantee delivery of all packets belongs to the same communication flow in an orderly manner under adaptive routing mode. In particular, we have proposed a flow-control policy based on a virtual circuit switch (VCS) method that exclusively won and reserve a virtual path for routing packets in an adaptive mode for each communication flow. To maximize network performance, we allow sharing of the reserved path among packets of different communication flows, routing under priority fix deterministic mode. The method saves need of having additional memory unit for storing all unordered packets while guaranteeing the packet’s ordering sequence at the destination end. An experiment conducted on two different size Mesh networks (8x8 and 12x12) under several synthetic traffic and benchmark application reveals that our virtual circuit switching (VCS) based proposed method offers a significant improvement over the state-of-the-art packet reordering method (ROR) and two similar type of research works. Our simulation based experimental result shows that method offers a 60% higher saturation point and 21% improvements (maximum) in throughput while offering a reduction of 60% in NoC area and 58% power value compared to the baseline reorder (ROR) method.

Security and privacy of UAV data using blockchain technology

The utility of virtual circuit (VC) based devices - UAVs, Drones, and similar other IoT based devices have gained immense momentum in the present day and age. These devices are predominantly used for aerial surveying in sensitive and remote areas. It is alarming that issues pertaining to stalking and information control have increased with the growth of technology. This paper presents a Blockchain Technology (BCT) based solution to improve the security and privacy of VC based device data. The proposed design is evaluated by implementing an IoT based application in a virtual vehicle monitoring system. The technical information about the instructions to the vehicle (devices), authentication, integrity, and vehicle reactions are stored in a cloud platform wherein Pentatope based Elliptic curve cryptography and SHA are used to ensure privacy in data storage. The data is later stored in an Ethereum based public blockchain to enable seamless BCT transactions. This system uses the Ganache platform for BCT that ensures data protection and privacy. Furthermore, metamask wallet for Ethbalance is required to perform transactions over BCT. The proposed methodology thus helps to protect data from stalkers, plaintext attacks as well as ciphertext attacks. The results, when compared with the state-of-the-art, justify the efficiency and security aspects of the proposed approach.

Flow-based anomaly intrusion detection using machine learning model with software defined networking for OpenFlow network

Moving towards recent technologies, Software Defined Networking (SDN) produces a promising network framework to combine the overall network management system with network programming. It gives a more effective tracking system towards the data center. By centralized system and symmetric controller, it prevents security cracks from creating new threats during OpenFlow packet transmission with vulnerabilities. It creates more interest to the researchers to work towards Flow-based SDN for the priority-driven algorithm in anomaly intruder detection. In this paper, we made a study towards a priority-based model using SDN to control the flow of data packets over the network, gives assurance to the bandwidth enforcement, and reallocation is made through virtual circuits. The network behavior of the system is continuously monitored through the machine learning model for normal and abnormal traffic data transmission to detect anomaly intruders. Flow-based machine learning (ML) model with SDN act as an intelligent system to limits the throughput virtually through the flow of reserved bandwidth and make use of extra bandwidth, which presents more than the utilization bandwidth for priority-based applications with minimal cost while compared with the traditional methods. The proposed work also compared with the schemes available at the network to produce outcomes with fast routing and the fault tolerance of existing networks to overcome the gap open at the security of the SDN architecture to detect and identify vulnerabilities.

Configurable activation function realized by non-linear memristor for neural network

The activation function is a crucial part for memristive neural networks. For the first time, we propose a memristor-based activation function by using the natural non-linear characteristics of the memristor itself. Compared to the virtual ground circuit in traditional memristive neural networks, the feedback resistance was replaced by the W/TaOx/Ru memristor with no additional expense. Simulation results demonstrate that the proposed memristor-based activation function can achieve a performance similar to that of traditional activation functions on the Mixed National Institute of Standards and Technology database. In addition, an improvement in the recognition rate of up to 2% can be obtained in different neuromorphic networks by modulating the non-linearity of the memristor. Furthermore, the memristor-based activation function can also receive a 94% recognition rate even considering the non-ideal factors of the device.

On the feasibility of using evolvable hardware for hardware Trojan detection and prevention

Evolvable hardware (EH) architectures are capable of changing their configuration and behavior dynamically based on inputs from the environment. In this paper, we investigate the feasibility of using EH to prevent Hardware Trojan Horses (HTHs) from being inserted, activated, or propagated in a digital electronic chip. HTHs are malicious hardware components that intend to leak secret information or cause malfunctioning at run-time in the chip in which they are integrated. We hypothesize that EH can detect internal circuit errors at run-time and reconfigure to a state in which the errors are no longer present. We implement a Virtual Reconfigurable Circuit (VRC) on a Field-Programmable Gate Array (FPGA) that autonomously and periodically reconfigures itself based on an Evolutionary Algorithm (EA). New VRC configurations are generated with an on-chip EA engine.We show that the presented approach is applicable in a scenario in which (1) the HTH-critical areas in the circuit are known in advance, and (2) the VRC is a purely combinatorial circuit, as opposed to the on-chip memory holding the golden reference, which requires one or more cycles to be read/written. We compare two different approaches for protecting the system against HTHs: Genetic Programming (GP) and Cartesian Genetic Programming (CGP). The paper reports on experiments on four benchmark circuits and gives an overview of both the limitations and the added value of the presented approaches.

Commutation error rapid compensation for brushless DC motor based on DC‐link current phase extraction method

In order to reduce the torque ripple and running loss caused by the commutation error in the brushless DC motor (BLDCM) of the magnetically suspended control moment gyroscope (MSCMG), this study proposes a novel method dealing with commutation error in sensorless controlled BLDCM by rapid phase extraction and compensation technique. First, a traditional virtual neutral point circuit consisted of three-phase resistance network and low-pass filter are used to obtain the zero-crossing points of the non-conducting phase back electromotive force without noise interference. Then, an improved phase extraction method is built after analysing the DC-link current. Commutation error is extracted from DC-link current with the improved phase extractor rapidly. Furthermore, the effect of speed offset caused by fluctuation during phase extraction is also analysed and an adaptive commutation error compensation method based on the DC-link current phase extraction is proposed. Finally, simulation and experimental results performed on the high-speed motor of MSCMG verify its effectiveness and rapidity. The main novelties of this study are the direct phase extraction algorithm with natural parameter insensitivity and robustness and the rapid iterative commutation error compensation method based on the extraction algorithm.

A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA

Evolvable hardware is a system that modifies its architecture and behavior to adapt with changes of the environment. It is formed by reconfigurable processing elements driven by an evolutionary algorithm. In this paper, we study a reconfigurable HexCell-based systolic array architecture for evolvable systems on FPGA. HexCell is a processing element with a tile-able hexagonal-shaped cell for reconfigurable systolic arrays on FPGAs. The cell has three input ports feed into an internal functional-unit connected to three output ports. The functional-unit is configured using dynamic partial reconfiguration (DPR), and the output ports, in contrast, are configured using virtual reconfiguration circuit (VRC). Our proposed architecture combines the merits of both DPR and VRC to achieve fast reconfiguration and accelerated evolution. A HexCell-based 4 × 4 array was implemented on FPGA and utilized 32.5% look-up tables, 31.3% registers, and 1.4% block RAMs of Artix-7 (XC7Z020) while same-size conventional array consumed 8.7%, 5.1%, and 20.7% of the same FPGA, respectively. As a case study, we used an adaptive image filter as a test application. Results showed that the fitness of the best filters generated by our proposed architecture were generally fitter than those generated by the conventional state-of-the-art systolic array on the selected application. Also, performing 900,000 evaluations on HexCell array was 2.6 × faster than the conventional one.

Hardware Evolution Based on Improved Simulated Annealing Algorithm in Cyclone V FPSoCs

Evolvable hardware (EHW) is an emerging area of research that uses evolutionary algorithms (EAs) to construct circuits without manual intervention. However, this technique confronts two major issues: the evolution efficiency of structures and the computational efficiency of EAs. To address these issues, we construct a novel virtual reconfigurable circuit (VRC) based on artificial neural network (ANN) architecture and develop a promising EA based on improved simulated annealing (ISA) for the research of EHW. Here, ISA escapes the local optimization through an inner loop and expands new search space through an outer loop. Furthermore, several strategies are proposed for the representation, perturbation and selection of solutions (individuals) to reduce the computational burden throughout the entire evolution process. The use of an Intel Cyclone V field programmable system-on-chip (FPSoC) further accelerates the execution of the algorithm and provides designers with much more high-level processing power than that provided by soft-cores. The obtained results show that the proposed method achieves high-speed processing and improves computational efficiency. The results also show that the method has good flexibility and scalability.

Hallucination Helps: Energy Efficient Virtual Circuit Routing

We consider virtual circuit routing protocols with an objective of minimizing energy in a network of components that are speed scalable, and that may be shut down when idle. We assume the standard model for component power: the power consumed by a component with load (speed) $s$ is $\sigma+ s^\alpha$, where $\sigma$ is the static power and the exponent $\alpha>1$. We obtain a very simple $O(\log^\alpha k)$-approximation algorithm for multicommodity routing, where $k$ is the number of demand pairs. This improves upon previous results by several logarithmic factors. The key step in our algorithm is a random sampling technique that we call hallucination, which is reminiscent of the sample-augment framework for buy-at-bulk problems, and sampling in cut-sparsification algorithms. We also consider the online setting of the problem, where demand pairs arrive over time. We show that our offline algorithm naturally extends to the online setting, and obtain a randomized competitive ratio of $\tilde{O}( \log^{3\alpha + 1} k)$, which is the first nontrivial bound. The analysis of this algorithm involves the study of priority multicommodity flows, where edges and demand-pairs have priorities and each demand-pair must route its flow only on edges of lower priority. We establish a polylogarithmic flow-cut gap for these priority flows, which we believe is of independent interest. Finally, we show how our technique can be used to achieve a randomized $( O(\log m), O(\log^2 m))$ bicriteria competitive algorithm for the uniform capacitated network design problem, where $m$ is the number of edges. Here, every edge has a cost $c_e$ and uniform capacity $q$, and the goal is to choose the minimum cost subgraph that can support the given multicommodity demand. This is the first online algorithm for this problem. In fact, our approach also improves prior results in the offline setting by several logarithmic factors.

Energy routing algorithm based on OSPF protocol and virtual circuit switching mode in energy local area network

Energy routing algorithm based on OSPF protocol and virtual circuit switching mode in energy local area network

Active-Damping Virtual Circuit Control for Grid-Tied Converters With Differential-Mode and Common-Mode Output Filters

This article presents a virtual circuit control method of designing a resonant-damping discrete-time controller for grid-tied voltage source converters with differential-mode (DM) and common-mode (CM) output filters. The method provides an intuitive way to specify the desired closed-loop behavior by means of a virtual reference circuit rather than abstract mathematical criteria such as closed-loop poles and weighting matrices. Therefore, the existing passive filter designs, which cannot be practically implemented due to excessive losses, and the well-established theory of filters can be exploited. The DM grid current and the CM capacitor voltage, which are the primary control objectives, inherit the main properties of their underlying virtual reference circuits, e.g., resonance damping and low-frequency behavior. On this account, to fortify the controller against grid impedance variations, a virtual circuit with a series resistor at the grid side is considered. Accordingly, the CM voltage and DM current controllers can be easily designed based on the low-frequency behavior of virtual circuits. The method can also be straightforwardly equipped with conventional controllers to enhance system performance, such as harmonic compensation. The simulation and experimental results verify the effectiveness of the DM and CM resonant damping and dynamic performance.

Experimental simulation of hybrid quantum systems and entanglement on a quantum computer

We propose the utilization of the IBM Quantum Experience quantum computing system to simulate different scenarios involving common hybrid quantum system components, the nitrogen vacancy center (NV center), and the flux qubit. We perform a series of simulation experiments and demonstrate properties of a virtual hybrid system, including its spin relaxation rate and state coherence. In correspondence with experimental investigations, we look at the scalability of such systems and show that increasing the number of coupled NV centers decreases the coherence time. We also establish the main error rate as a function of the number of control pulses in evaluating the fidelity of the four qubit virtual circuit with the simulator. Our results show that the virtual system can attain decoherence and fidelity values comparable to what has been reported for experimental investigations of similar physical hybrid systems, observing a coherence time at 0.35 s for a single NV center qubit and fidelity in the range of 0.82. This work thus establishes an effective simulation protocol to test and evaluate different technologies as a supplementary measure that complements their experimental operation.

Realization of Sequential Control Function Based on Bay Level Equipment in Smart Substation

In view of the problem of low reliability and automation of advanced application functions such as sequential control in smart substation, the logic configuration mode of sequential control is analyzed based on the principle of logic virtual circuit of bay level equipment in smart substation, and the realization of sequential control function based on bay level equipment is proposed. This method improves the operational reliability and configuration flexibility of sequential control, and fundamentally solves the technical application problem, so as to improve the intelligent level of power grid.

Qubit allocation as a combination of subgraph isomorphism and token swapping

In 2016, the first quantum processors have been made available to the general public. The possibility of programming an actual quantum device has elicited much enthusiasm. Yet, such possibility also brought challenges. One challenge is the so called Qubit Allocation problem: the mapping of a virtual quantum circuit into an actual quantum architecture. There exist solutions to this problem; however, in our opinion, they fail to capitalize on decades of improvements on graph theory. In contrast, this paper shows how to model qubit allocation as the combination of Subgraph Isomorphism and Token Swapping. This idea has been made possible by the publication of an approximative solution to the latter problem in 2016. We have compared our algorithm against five other qubit allocators, all independently designed in the last two years, including the winner of the IBM Challenge. When evaluated in "Tokyo", a quantum architecture with 20 qubits, our technique outperforms these state-of-the-art approaches in terms of the quality of the solutions that it finds and the amount of memory that it uses, while showing practical runtime.

Logic Synthesis of Approximate Circuits

The ability of several important application domains to tolerate inexactness or approximations in a large fraction of their computations has lead to the advent of approximate computing , a new design paradigm that exploits the intrinsic error-resilient nature to optimize computing platforms for energy and performance. A promising approach to approximate computing is to design approximate circuits, or circuit implementations that are highly efficient but differ in functionality from their original specifications subject to a prespecified quality constraint. While a slew of manual design techniques for approximate circuits have demonstrated their significant potential, a key requirement for their mainstream adoption is to develop automatic methodologies and tools that are general and scalable to any given circuit and quality specification. In this article, we propose SALSA, a systematic methodology for automatic logic synthesis of approximate circuits. Given a golden RTL specification of a circuit and a quality constraint that defines the amount of error that may be introduced in the implementation, SALSA synthesizes an approximate version of the circuit that adheres to the prespecified quality bounds. We make two key contributions: 1) the rigorous formulation of the problem of approximate logic synthesis (ALS), enabling the generation of circuits that is corrected by construction and 2) mapping the problem of approximate synthesis into an equivalent traditional logic synthesis problem, thereby allowing the capabilities of existing synthesis tools to be fully utilized for ALS. In order to achieve these benefits, SALSA forms a virtual quality constraint circuit (QCC) that encodes the quality constraints using logic functions called Q-functions . It then captures the flexibility that engendered by them as approximation don’t cares (ADCs), which are used for circuit simplification using traditional don’t care-based optimization techniques. We utilized SALSA to automatically synthesize approximate circuits ranging from arithmetic building blocks (adders, multipliers, and MAC) to entire datapaths (DCT, FIR, IIR, SAD, FFT Butterfly, and Euclidean distance), demonstrating scalability and significant improvements in area ( $1.1\times $ to $1.85\times $ for tight error constraints, and $1.2\times $ to $4.75\times $ for relaxed error constraints) and power ( $1.15\times $ to $1.75\times $ for tight error constraints, and $1.3\times $ to $5.25\times $ for relaxed error constraints).