Virtex-5 Device Research Articles

High throughput implementation of SHA3 hash algorithm on field programmable gate array (FPGA)

Cryptographic hash function is an essential element in sensitive communications, such as banking, military and health. It ensures secure communication by checking data integrity, storing passwords and other important roles. Keccak hash function (i.e. SHA3) is the best one in terms of resistance against recent cryptanalysis attacks as well as of hardware performance. However, an efficient improvement in terms of hardware performance is always needed, such as increasing speed or decreasing area consumption. In this paper, we have focused on improving the speed (throughput) of Keccak hash algorithm by proposing a new design which is based on decreasing the number of clock cycles needed to produce a hash value. Consequently, we could achieve 33.35 Gbps as a highest achieved throughput. However, a decrease in terms of maximum frequency has been noticed. Our design has been implemented in Xilinx Virtex5 and Virtex6 FPGA device, and has been compared to recent published implementations.

Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising

In recent years, Finite Impulse Response (FIR) filter plays a major role in signal processing applications. Earlier many research papers are described the different types of FIR filter design. But, none of the paper explained about signal denoising application with an effective multiplier design. In this paper, Vedic Design - Carry Lookahead Adder FIR filter architecture is introduced to perform the FIR filter operation with Electro Cardiogram (ECG) signal de-noising application. By usingthe MATLAB program, the input ECG signal is read and Additive White Gaussian Noise (AWGN) is added to the input signal. The denoising process is implemented in Verilog and the obtained output is written in text files. For de-noising the signal, the binary text values are read in MATLAB. With the help of Verilog code, FPGA performance (LUT, flip flop, slices, and frequency) and ASIC performance (area, power, and delay) are evaluated. For ASIC implementation, 180 nm and 45 nm technology are used and for FPGA implementation Virtex-4, Virtex-5, and Virtex-6 devices are used to evaluate the performance. The Mean Square Error (MSE), Bit Error Rate (BER), and Signal to Noise Ratio (SNR) performance are calculated from the de-noised signal. In 180 nm technology, 42.39% of the area, 29.53% of delay, 43.89% of APP, 70.41% of ADP reduced in VD-CLA-FIR. In 45 nm technology, 13.2% of the area, 32.25% of the delay, 24.37% of APP, and 39.02% of ADP reduced in VD-CLA-FIR method compared to the conventional methods.

A Novel Reconfigurable Orthogonal Frequency Division Multiplexing Transceiver

As the world moves toward 3G/4G there is a need for high data rate and relatively wide bandwidths. OFDM (Orthogonal Frequency Division Multiplexing) a form of multicarrier modulation technique is widely used to achieve high speed efficient data transmission at the rate of several Mbps. It is used in Wi-Fi standards like 802.11a, 802.11n, 802.11ac, broadcast standards like Digital Video Broadcast (DVB) and cellular telecommunications standard LTE. The main advantage of OFDM compared to single carrier modulation is their robustness to channel fading in wireless environment, high baud rates and less inter symbol interference. One major disadvantage is its High PAPR. PTS partial transmit sequences (PTS) and selective mapping are proposed to reduce it. Since FFT is core block of OFDM it must be able to adapt itself to ever changing digital world. A function specific reconfigurable 2k SDF (Single path delay feedback) FFT is proposed. It utilizes less power and can be configured for different FFT sizes ranging from 16-point to 1024-point. The validity and efficiency of the architecture have been verified by simulation in hardware description language VERILOG and targeted on Virtex-6 device. Finally PAPR is estimated by MATLAB simulation.

Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification

Road sign recognition is part of the automatic driver assistance systems implemented on the dashboard of vehicles. The recognition task is often carried out based on a classification procedure manipulating the detected signs. Classification tasks can be resolved by the use of multilayer artificial neural network systems. This article proposes an optimized real-time on-chip hardware implementation of multilayer perceptron system used for road sign classification. Four architectural approaches were described: on the one hand, the classic and the serial optimized architectures that offer a very significant reduction in hardware resources, and, on the other hand, the parallel and the optimized architectures, which offer a much reduced, time execution. In order to benefit from the advantages of the allocated hardware resources and the classification of the runtime process, these four architectures have been implemented on field programmable gate array Virtex-6 devices and their performances were quantified and evaluated according to a cost criterion. The energy dissipated by each of these architectures was measured; the achieved results have allowed us to conclude that the serial optimized architecture is the optimal solution, since it creates a tradeoff between the low cost, and the energy efficiency, and still real-time for the considered application.

Design of high performance filter bank multi-carrier transmitter

Filter bank multi-carrier (FBMC) is very important to achieve high spectral efficiency in the wireless communication process. Previously, orthogonal frequency division multiplexing (OFDM) technique is used to obtain a high spectral efficiency. But area, power and delay is high than the FBMC transmitter technique. The main aim of this work is to design an optimized FBMC transmitter for high speed, low power and low area applications. There is a tradeoff between power and speed. To overcome this challenge, a new compact FBMC transmitter will be introduced in the paper. Generally, the FBMC transmitter consists of serial to parallel converter, QAM modulation, inverse FFT, parallel to serial converter and filter. The existing FBMC transmitter is designed by using inverse radix 2 FFT and poly phase filter. It requires more area, power and delay. To overcome this problem, a new radix2 multipath delay commutator (R2MDC) based inverse FFT and multiple constant multiplication (MCM) based FIR filter are used in the proposed FBMC transmitter. Because MCM based FIR filter doesn’t needs multiplier structure. The multiplication process is done by shift, add and subtract operation. Hence area and power is low in MCM based FIR filters, when compared to poly base filter. Also R2MDC FFT is used for high speed application. Comparison between conventional FBMC transmitter and proposed FBMC transmitter is carried out to analyze the performance, area, complexity and power. Also the functionality of FBMC transmitter is verified by using Xilinx ISE Virtex5 device. From the comparison results, it shows that the proposed FBMC transmitter offers 17% average area, delay and power (ADP) product than the existing FBMC transmitter.

High performance and energy efficient single‐precision and double‐precision merged floating‐point adder on FPGA

A high performance and energy efficient single-precision and double-precision merged floating-point adder based on the two-path FP addition algorithm designed and implemented on field programmable gate array (FPGA) is presented. With a fully pipelined architecture, the proposed adder can accomplish one double-precision addition or two parallel single-precision additions in six clock cycles. The proposed architecture is designed based on the double-precision adder and each major component is segmented to support dual single-precision operations. In addition, all the components of the proposed adder are optimised for mapping on FPGA. The proposed architecture is implemented on both Altera Stratix-III and Xilinx Virtex-5 devices and it has a faster clock frequency when compared with the double-precision intellectual property (IP) core adder provided by the FPGA vendors. Since the dual single-precision operations support, the proposed adder has higher throughput compared with the single-precision IP core adder. In addition, the proposed adder has better energy efficiency compared with both single-precision and double-precision IP core adder. The implementation results of the proposed adder on the latest Altera Arria-10 and Xilinx Virtex-7 devices are provided. A direct implementation of the proposed architecture on STM-90 nm technology ASIC platform is also performed.

Customizable embedded processor array for multimedia applications

We are proposing a Customizable Embedded Processor Array for Multimedia Applications (CPAMA). This architecture can be used as a standalone image/video processing chip in consumer electronics. Its building blocks are all designed to achieve low power and low area, thus it is a good candidate for low cost consumer electronics. Our contribution is, designing a configurable embedded multimedia processor array considering the nature of image/video processing applications. This approach is considered in all the basic blocks of the architecture. Because of its configurable architecture and ability to connect with other devices, it may be used in a large domain of applications. Our architecture is purely implemented with VHDL. It is not dependent on any technology or design software. We have implemented our architecture for different applications on a Xilinx Virtex-5 device and as a number of Application Specific Integrated Circuits (ASIC) by using 90nm CMOS technology. Experimental case studies show that CPAMA has better or comparable results to the existing similar architectures in terms of performance and energy consumption. Our studies show that throughput of CPAMA is 0.3x–2.4x times better than ADRES. Energy consumption of CPAMA is 31–50% less than ADRES. On the other hand, in one configuration of IDCT application, CPAMA provides 56% less throughput and consumes 55% more energy than ADRES.

Area‐ and power‐efficient iterative single/double‐precision merged floating‐point multiplier on FPGA

In this study, an area and power-efficient iterative floating-point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single-precision (SP) and double-precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied when mapping the mantissa multiplier in order to reduce the number of digital signal processing (DSP) blocks required. For DP operations, the iterative method is applied which require much less hardware than a fully pipelined DP multiplier and thus reduces the power consumption. To further reduce the power consumption, the unused logic blocks for a specific operation mode are disabled. Compared to previous work, the proposed multiplier can achieve 33% reduction of DSP blocks, 4.3% less look-up tables (LUTs), and 31.2% less flip-flops while having 4% faster clock frequency on Virtex-5 devices. Compared to the intellectual property core DP multiplier provided by the FPGA vendors, the proposed multiplier required less DSP blocks and achieves lower-power consumption. The mapping solutions and implementation results of the proposed multiplier on Xilinx Virtex-7 and Altera Arria-10 devices are also presented. In addition, the results of a direct implementation of the proposed architecture on STM-90 nm ASIC platform are reported.

Efficient FPGA Mapping of Pipeline SDF FFT Cores

In this paper, an efficient mapping of the pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture to field-programmable gate arrays (FPGAs) is proposed. By considering the architectural features of the target FPGA, significantly better implementation results are obtained. This is illustrated by mapping an R22SDF 1024-point FFT core toward both Xilinx Virtex-4 and Virtex-6 devices. The optimized FPGA mapping is explored in detail. Algorithmic transformations that allow a better mapping are proposed, resulting in implementation achievements that by far outperforms earlier published work. For Virtex-4, the results show a 350% increase in throughput per slice and 25% reduction in block RAM (BRAM) use, with the same amount of DSP48 resources, compared with the best earlier published result. The resulting Virtex-6 design sees even larger increases in throughput per slice compared with Xilinx FFT IP core, using half as many DSP48E1 blocks and less BRAM resources. The results clearly show that the FPGA mapping is crucial, not only the architecture and algorithm choices.

Fast Algorithms and Architectures for 8-Point DST-II/DST-VII Approximations

Multiplier-free fast algorithms are derived and analyzed for realizing the 8-point discrete sine transform of type II and type VII (DST-II and DST-VII) transforms with applications in image and video compression. A new fast algorithm is identified using numerical search methods for approximating DST-VII without employing multipliers. In addition, recently proposed fast algorithms for approximating the 8-point DCT-II are now extended to approximate DST-II. All proposed approximations for DST-II and DST-VII are compared with ideal transforms, and circuit complexity is measured using FPGA-based rapid prototypes on a 90[Formula: see text]nm Xilinx Virtex-4 device. The proposed architectures find applications in emerging video processing standards such as H.265/HEVC.

LVQ neural network optimized implementation on FPGA devices with multiple-wordlength operations for real-time systems

The development of hardware platforms for artificial neural networks (ANN) has been hindered by the high consumption of power and hardware resources. In this paper, we present a methodology for ANN-optimized implementation, of a learning vector quantization (LVQ) type on a field-programmable gate array (FPGA) device. The aim was to provide an intelligent embedded system for real-time vigilance state classification of a subject from an analysis of the electroencephalogram signal. The present approach consists in applying the extension of the algorithm architecture adequacy (AAA) methodology with the arithmetic accuracy constraint, allowing the LVQ-optimized implementation on the FPGA. This extension improves the optimization phase of the AAA methodology by taking into account the operations wordlength required by applying and creating approximative-wordlength operation groups, where the operations in the same group will be performed with the same operator. This LVQ implementation will allow a considerable gain of circuit resources, power and maximum frequency while respecting the time and accuracy constraints. To validate our approach, the LVQ implementation has been tried for several network topologies on two Virtex devices. The accuracy–success rate relation has been studied and reported.

Efficient FPGA implementation of AES 128 bit for IEEE 802.16e mobile WiMax standards

In an advancement of communication field, wireless technology plays a predominant role in data transmission. In the timeline of wireless domain, Wi-Fi, Bluetooth, zigbee etc are some of the standards, which are being used in today’s wireless medium. In addition, the WiMax is introduced by IEEE in IEEE 802.16 for long distance communication, specifically 802.16e standard for mobile WiMax. It is an acronym of Worldwide Interoperability for Microwave Access. It is to be deliver wireless transmission with high quality of service in a secured environment. Since, security becomes dominant design aspect of every communication, a new technique has been proposed in wireless environment. Privacy across the network and access control management is the goal in the predominant aspects in the WiMax protocol. Especially, MAC sub layer should be evaluated in the security architecture. It has been proposed on cryptography algorithm AES that require high cost. Under this scenario, we present the optimized AES 128 bit counter mode security algorithm for MAC layer of 802.16e standards. To design a efficient MAC layer, we adopt the modification of security layers data handling process. As per the efficient design strategy, the power and speed are the dominant factors in mobile device. Since we concentrate mobile WiMax, efficient design is needed for MAC Security layer. Our proposed model incorporates the modification of AES algorithm. The design has been implemented in Xilinx virtex5 device and power has been analyzed using XPower analyzer. This proposed system consumes 41% less power compare to existing system.

FPGA Implementation of Novel Real Time Distributed Canny Edge Detection Algorithm

Digital image processing is an ever expanding and dynamic area with applications reaching out into everyday life such as medicine, space exploration, surveillance and many more areas. These applications involve different processes like image enhancement and edge detection. Among different edge detectors that are available, the Canny edge detector has better edge detection performance because it satisfies three main criteria: low error rate, good localization and minimal response. But this edge detector suffers from high latency because the algorithm is based on frame-level statistics. To decrease the latency, an algorithm called Distributed Canny edge detection algorithm is developed in which the algorithm is based upon block-level statistics. Even though the distributed Canny edge detection algorithm produces better edge detection performance with reduced latency, the FPGA implementation of it requires hardware components to realize the architecture. To solve this problem, we present a novel real-time distributed Canny edge detection algorithm which does not require any hardware components to realize the architecture in FPGA. In this paper, the proposed algorithm at block-level is implemented in FPGA which adaptively calculates the high and low thresholds based on the block type and local distribution of the gradients in a block. This design is coded in VHDL and synthesized on Xilinx Virtex-5 device (XC5VLX330T) using Xilinx's ISE software. The evaluations show that proposed algorithm is scalable, has significantly reduced latency almost 50% of original Canny algorithm and area efficient. The enhanced edge detection performance is compared to the existing frame-level Canny. Finally, the proposed algorithm is also used to detect cancer cells in ultrasound lung image and tested using ModelSim. This proves that proposed distributed Canny edge detection algorithm can be efficiently used in real-time image processing also.

Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA.

This paper describes two novel time-to-digital converter (TDC) architectures. The first is a dual-phase tapped-delay-line (TDL) TDC architecture that allows us to minimize the clock skew problem that causes the highly nonlinear characteristics of the TDC. The second is a pipelined on-the-fly calibration architecture that continuously compensates the nonlinearity and calibrates the fine times using the most up-to-date bin widths without additional dead time. The two architectures were combined and implemented in a single Virtex-6 device (ML605, Xilinx) for time interval measurement. The standard uncertainty for the time intervals from 0 to 20 ns was less than 12.83 ps-RMS (root mean square). The resolution (i.e., the least significant bit, LSB) of the TDC was approximately 10 ps at room temperature. The differential nonlinearity (DNL) values were [-1.0, 1.91] and [-1.0, 1.88] LSB and the integral nonlinearity (INL) values were [-2.20, 2.60] and [-1.63, 3.93] LSB for the two different TDLs that constitute one TDC channel. During temperature drift from 10 to 50(°)C, the TDC with on-the-fly calibration maintained the standard uncertainty of 11.03 ps-RMS.

AC_ICAP: A Flexible High Speed ICAP Controller

The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

Realisation of AWGN Channel Emulation Modules Under SISO and SIMO Environments for 4G LTE Systems

The testing of a wireless transmitter and receiver in the real-world channel is tedious. So, a channel emulator using FPGA helps in the testing of transmitter and receiver by providing a test environment that simulates a real-world wireless channel. Since FPGAs are flexible, cheap and reconfigurable, they are used in designing an AWGN channel emulator for 4G LTE for Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) environments. In this paper, three basic modules: transmitter, channel estimation and receiver modules are synthesized. In the transmitter module, the input data is 64QAM modulated and transmitted into the channel. In the channel estimation module, the transmitter data gets multiplied with the channel coefficients and then added with the noise present in the channel. In the receiver module, the data is detected using MMSE estimation. These are implemented in Virtex-5 device using PlanAhead tool and the Resource and Power Estimations are discussed.

An FPGA-based parallel architecture for on-line parameter estimation using the RLS identification algorithm

A parallel architecture for an on-line implementation of the recursive least squares (RLS) identification algorithm on a field programmable gate array (FPGA) is presented. The main shortcoming of this algorithm for on-line applications is its computational complexity. The matrix computation to update error covariance consumes most of the time. To improve the processing speed of the RLS architecture, a multi-stage matrix multiplication (MMM) algorithm was developed. In addition, a trace technique was used to reduce the computational burden on the proposed architecture. High throughput was achieved by employing a pipelined design. The scope of the architecture was explored by estimating the parameters of a servo position control system. No vendor dependent modules were used in this design. The RLS algorithm was mapped to a Xilinx FPGA Virtex-5 device. The entire architecture operates at a maximum frequency of 339.156MHz. Compared to earlier work, the hardware utilization was substantially reduced. An application-specific integrated circuit (ASIC) design was implemented in 180nm technology with the Cadence RTL compiler.

Hardware and Software Co-design: An Architecture Proposal for a Network-on-Chip Switch based on Bufferless Data Flow

Abstract The use of on chip networks as interconnection media for systems implemented in FPGAs is limited by the amount of logical resources necessary to deploy the network in the target device, and the time necessary to adjust the network parameters to achieve the performance goal for the system. In this paper we present a switch architecture, with data flow control based on circuit switching and aimed for on-chip networks with a Spidergon topology, which seeks to reduce the area occupied without severely affecting the overall network performance. As a result, we obtained a switch that requires only 114 slices in its most economic version on a Virtex 4-device. We also provide a performance profile, obtained by subjecting a network formed by these switches to different synthetic workloads within a simulator. This simulator was developed as part of the design flow of the switch, and it proves to be an essential tool for the test and validation process.

Fast hardware architecture for grey‐level image morphology with flat structuring elements

Mathematical morphology operators, applied in many vision-based applications, are characterised by repetitive operations on large amounts of data. Thus, novel design strategies for efficient hardware implementations are necessary. This study presents and evaluates a real-time hardware architecture for grey-level image erosion and dilation that processes data in streams for an efficient utilisation of memory bandwidth and low on-chip memory requirements. A low-complexity and highly modular architecture is proposed based on a sequence of pipeline stages, and parallel processing in order to minimise computational times. The design is intended to be used as a hardware accelerator in real-time embedded image processing applications requiring moderate-size and non-rectangular flat structuring elements on high-resolution images. The architecture is prototyped on a field programmable gate array device operating at a clock frequency of 260 MHz on a Virtex-6 device which compares favourably to the well-known delay-line-based hardware architectures in terms of complexity, memory requirements and execution time. A 7 × 7 dilation/erosion operator on 1280 × 1024 grey-level image can be performed at a rate of 95 frames per second, but the architecture can be scaled up if required.

Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA

The cryptographic hash functions BLAKE and Skein are built from the ChaCha stream cipher and the tweakable Threefish block cipher, respectively. Interestingly enough, they are based on the same arithmetic operations, and the same design philosophy allows one to design lightweight coprocessors for hashing and encryption. The key element of our approach is to take advantage of the parallelism of the algorithms considered in this work to deeply pipeline our Arithmetic and Logic Units, and to avoid data dependencies by interleaving independent tasks. We show for instance that a fully autonomous implementation of BLAKE and ChaCha on a Xilinx Virtex-6 device occupies 144 slices and three memory blocks, and achieves competitive throughputs. In order to offer the same features, a coprocessor implementing Skein and Threefish requires a substantial higher slice count.