Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising

Abstract

In recent years, Finite Impulse Response (FIR) filter plays a major role in signal processing applications. Earlier many research papers are described the different types of FIR filter design. But, none of the paper explained about signal denoising application with an effective multiplier design. In this paper, Vedic Design - Carry Lookahead Adder FIR filter architecture is introduced to perform the FIR filter operation with Electro Cardiogram (ECG) signal de-noising application. By usingthe MATLAB program, the input ECG signal is read and Additive White Gaussian Noise (AWGN) is added to the input signal. The denoising process is implemented in Verilog and the obtained output is written in text files. For de-noising the signal, the binary text values are read in MATLAB. With the help of Verilog code, FPGA performance (LUT, flip flop, slices, and frequency) and ASIC performance (area, power, and delay) are evaluated. For ASIC implementation, 180 nm and 45 nm technology are used and for FPGA implementation Virtex-4, Virtex-5, and Virtex-6 devices are used to evaluate the performance. The Mean Square Error (MSE), Bit Error Rate (BER), and Signal to Noise Ratio (SNR) performance are calculated from the de-noised signal. In 180 nm technology, 42.39% of the area, 29.53% of delay, 43.89% of APP, 70.41% of ADP reduced in VD-CLA-FIR. In 45 nm technology, 13.2% of the area, 32.25% of the delay, 24.37% of APP, and 39.02% of ADP reduced in VD-CLA-FIR method compared to the conventional methods.