FPGA Implementation of Novel Real Time Distributed Canny Edge Detection Algorithm

Abstract

Digital image processing is an ever expanding and dynamic area with applications reaching out into everyday life such as medicine, space exploration, surveillance and many more areas. These applications involve different processes like image enhancement and edge detection. Among different edge detectors that are available, the Canny edge detector has better edge detection performance because it satisfies three main criteria: low error rate, good localization and minimal response. But this edge detector suffers from high latency because the algorithm is based on frame-level statistics. To decrease the latency, an algorithm called Distributed Canny edge detection algorithm is developed in which the algorithm is based upon block-level statistics. Even though the distributed Canny edge detection algorithm produces better edge detection performance with reduced latency, the FPGA implementation of it requires hardware components to realize the architecture. To solve this problem, we present a novel real-time distributed Canny edge detection algorithm which does not require any hardware components to realize the architecture in FPGA. In this paper, the proposed algorithm at block-level is implemented in FPGA which adaptively calculates the high and low thresholds based on the block type and local distribution of the gradients in a block. This design is coded in VHDL and synthesized on Xilinx Virtex-5 device (XC5VLX330T) using Xilinx's ISE software. The evaluations show that proposed algorithm is scalable, has significantly reduced latency almost 50% of original Canny algorithm and area efficient. The enhanced edge detection performance is compared to the existing frame-level Canny. Finally, the proposed algorithm is also used to detect cancer cells in ultrasound lung image and tested using ModelSim. This proves that proposed distributed Canny edge detection algorithm can be efficiently used in real-time image processing also.