Very Large Scale Integration Interconnects Research Articles

A Very Large-Scale Integration Global Routing Optimization Model for Hybrid Physarum Bionetworks

Interconnection of billion transistors in a single layer of a die with the advent of the nanometer regime imposes a great challenge to handle the increased complexity, particularly in the global routing of the Very Large-Scale Integration (VLSI) physical design phase which involves distinct optimization in the computation of overall interconnect wire-length. In classical graph theory, the VLSI global routing problem can be mapped as a Rectilinear Steiner Minimal Tree (RSMT) Problem, which in itself is an NP-complete problem. The use of metaheuristics in solving this problem plays a major role where Ant Colony Optimization (ACO) and Particle Swarm Optimization (PSO) proved to be efficient algorithms. Both algorithms face certain limitations and inconsistencies in determining maximum optimization. A new optimization algorithm with insight from the biological activity of microorganisms has been proposed in this paper which is based on the behavior of the unicellular organism Physarum Polycephalum aiming at minimizing the wire length of VLSI interconnects. The paper further explores a new hybridization technique employing the use of Physarum BioNetwork and Particle Swarm Optimization together where PSO generate better possible Steiner’s in the initial stage for the final process using Physarum BioNetwork to ensure better convergence. Complexity analysis of the proposed algorithm has been performed and the simulation results achieved greater efficiency when compared with the conventional PSO algorithm and available industry benchmark over-optimizing Global Routing problem in VLSI design.

A Theoretical Modeling of Adaptive Mixed CNT Bundles for High-Speed VLSI Interconnect Design

The aroused quest to reduce the delay at the interconnect level is the main urge of this paper, so as to come across a configuration of carbon nanotube (CNT) bundles, namely, squarely packed bundles of mixed CNTs. The demonstrated approach in this paper makes the mixed CNT bundle adaptable to adopt for high-speed very-large-scale integration (VLSI) interconnects with technology shrinkage. To reduce the delay of the proposed configuration of the mixed CNT bundle, the behavioral change of resistance (R), inductance (L), and capacitance (C) has been observed with respect to both the width of the bundle and the diameter of the CNTs in the bundle. Consequently, the performance of the modified bundle configuration is compared with a previously developed configuration, namely, squarely packed bundles of dimorphic MWCNTs in terms of propagation delay and crosstalk delay at local-, semiglobal-, and global-level interconnects. The proposed bundle configuration is, ultimately, enacted as the better one for 32-nm and 16-nm technology nodes, and is suitable for 7-nm nodes as well.

Evaluation and Reduction of Signal Integrity Issues in Multiwalled Carbon Nanotube On-Chip VLSI Interconnects

Due to advancements in device scaling in very-large-scale integration (VLSI) technology, signal integrity (SI) issues play a major role to determining the performance of on-chip interconnects in high-speed digital circuits. The main SI issues are delays, peak voltage noise effects, crosstalk, and timing uncertainties. Here, the SI issues of the coupled multi-walled carbon nanotube (MWCNT) on-chip interconnects are evaluated with and without the effect of shielding technique and compared to the copper interconnects. The MWCNT exhibits an average of 47.9% smaller propagation delays than Cu in dynamic crosstalk conditions. Further, for crosstalk reduction, the active shielding (AS) and passive shielding (PS) techniques are proposed. With the AS and PS techniques, the MWCNT interconnects experience a decreased delay by 46.8% and 30.15% compared to without shielding technique, respectively. Moreover, the AS exhibits smaller crosstalk effects than the PS technique due to its input switching activities on shielded lines. In addition, the quality of the signal (QoS) and Intersymbol interference (ISI) noise effects of coupled MWCNT interconnect with and without shielding is evaluated. Finally, to improve the QoS and reduce the ISI effects, the decision feedback equalizer with the least mean square adaptive algorithm is implemented at the receiver end.

A PSO based optimal repeater insertion technique for carbon nanotube interconnects

ABSTRACT Optimal repeater insertion is important in VLSI(very large scale integration) interconnects to reduce propagation delay and power dissipation. We propose a particle swarm optimisation (PSO)-based optimal repeater number for different lengths of carbon nanotube (CNT) interconnects at 20 nm and 14 nm technology nodes. First, numerical equations for optimal repeaters are modelled. Secondly, a PSO-based algorithm is developed and various input parameters are used to train the PSO. Optimal number of repeaters and the propagation delay for CNT interconnects for lengths ranging from 500 to 2000 µm are found out. Results are compared for both numerical and PSO methods, and it is found that they are within 2% deviation. Although earlier work shows similar findings, we have used CNTFET(carbon nanotube field effect transistor)-based inverters as repeaters in CNT interconnects for the first time. We have carried out the analysis for two values of repeater size, i.e. h = 50 and 75.

Effect of Thermal Boundary Resistance between the Interconnect Metal and Dielectric Interlayer on Temperature Increase of Interconnects in Deeply Scaled VLSI.

Temperature increase in the continuously narrowing interconnects accelerates the performance and reliability degradation of very large scale integration (VLSI). Thermal boundary resistance (TBR) between an interconnect metal and dielectric interlayer has been neglected or treated approximately in conventional thermal analyses, resulting in significant uncertainties in performance and reliability. In this study, we investigated the effects of TBR between an interconnect metal and dielectric interlayer on temperature increase of Cu, Co, and Ru interconnects in deeply scaled VLSI. Results indicate that the measured TBR is significantly higher than the values predicted by the diffuse mismatch model and varies widely from 1 × 10-8 to 1 × 10-7 m2 K W-1 depending on the liner/barrier layer used. Finite element method simulations show that such a high TBR can cause a temperature increase of hundreds of degrees in the future VLSI interconnect. Characterization of interface properties shows the significant importance of interdiffusion and adhesion in TBR. For future advanced interconnects, Ru is better than Co for heat dissipation in terms of TBR. This study provides a guideline for the thermal management in deeply scaled VLSI.

Mathematical Framework of Tetramorphic MWCNT Configuration for VLSI Interconnect

Having a 1D material like Multiwall Carbon Nanotube (MWCNT) as a potential candidate for high speed Very Large Scale Integration (VLSI) interconnect creates a good scope to reduce the delay by estimating the parasitic elements i.e. Resistance ( $R$ ), Inductance ( $L$ ) and Capacitance ( $C$ ) properly. We have contrived an innovative configuration namely Tetramorphic (TM) for the bundle of MWCNTs with four different diameters. We have focused on 45 nm, 22 nm, 11 nm and 7 nm technology nodes to justify the novelty of our proposed configuration over the existing MWCNT bundle configurations. Having the parasitic $RLC$ elements for a specific technology node, the diameter optimization took place in this work. Subsequently, we obtain the propagation delay results for local, semi-global and global level interconnect. Finally, we compare the results with the other existing configuration to show the supremacy of our introduced configuration for MWCNT bundle to explore high speed VLSI interconnect and represent crosstalk delay and power dissipation. Moreover, this configuration is highly dense which will offer the size shrinkage feature in a substantial manner.

Comparative Analysis of Mixed CNTs and MWCNTs as VLSI Interconnects for Deep Sub-micron Technology Nodes

This research paper presents a performance analysis of the mixed carbon nanotube (CNT) as an interconnect for very large-scale integration (VLSI) circuits at deep sub-micron (DSM) technology nodes. The mixed CNT interconnect is a combination of multiwall CNTs (MWCNTs) and single-walled CNTs (SWCNTs). Using hierarchical modeling, a multiconductor circuit model is proposed for the mixed CNT bundle at global-level interconnect lengths. Due to the insertion of SWCNTs in a MWCNT interconnect, the overall density of the conducting tubes in the proposed mixed CNT interconnect structure increases, thereby decreasing the overall resistance and inductance of the mixed CNTs. The performance of the proposed mixed CNT interconnect is estimated in terms of delay and power delay product (PDP) for different technology nodes (32 nm, 22 nm, and 16 nm) at different interconnect lengths. For comparative analysis, a similar analysis is performed using MWCNT bundle interconnects. The comparative results show that there is reduction in the overall propagation delay and PDP for the proposed mixed CNTs compared to MWCNTs as the interconnect material for DSM technology nodes at global-level interconnect lengths.

Metal on Graphenated Metal for VLSI Interconnects

AbstractCopper is running out of steam for modern very large scale integration (VLSI) technology and therefore there is a need for paradigm shift to a more reliable interconnect structure. Metal–graphene–metal structure is suggested to be a suitable candidate. A new method is devised wherein graphene synthesized on copper foil can act as a reducing agent for electroless plating of copper without the need of any other chemical species, making such novel interconnect structure feasible in practice. The superiority of such interconnect structure can be seen both experimentally and simulationally. Such deposition is also possible for synthesized or transferred graphene on other metals such as nickel, titanium, aluminum, gold, silver, cobalt, palladium, having metal–graphene interface separation of less than 3.2–3.6 Å as derived from its fundamental principle.

Analytical Modeling of Electromigration Failure for VLSI Interconnect Tree Considering Temperature and Segment Length Effects

Electromigration (EM) is a major concern for very large-scale integration (VLSI) interconnect reliability, particularly for interconnect trees with multibranch metal wires representing continuously connected metal (Cu) lines terminated at diffusion barriers. For EM modeling and assessment, one important problem is to perform fast EM time to failure analysis for practical VLSI chips. Compact modeling for EM effects for the interconnect tree has been studied recently to better EM signoff analysis. But the existing method cannot consider wires stressed under time-varying temperature, which is very typical for practical chip working conditions. In this paper, we develop the exact analytic model for the stress evolution of interconnect trees under different current density and varying segment length from the first principle. Due to the difficulty in obtaining the exact analytical solution, we focus on three-terminal wire in this paper. The stress evolution is modeled by two Korhonen’s equations coupled through boundary conditions which are solved with the Laplace transformation technique. The new analytical EM model is further extended to consider the time-varying temperature stressing condition and initial non-zero residual stress. The proposed method is compared with the finite-element method (FEM) tool COMSOL, the recently proposed eigenfunction-based method, and the published EM simulator XSim. The comparison shows that the analytical solution agrees well with the results from the FEM numerical analysis. It uses much fewer terms compared to the eigenfunction method for the same accuracy. It also agrees very well with XSim, which is consistent with the previously reported measured results.

Capacitance of Graphene/Copper Hybrid Nano Ribbon Interconnect - a First Principle Study

In very large scale integration (VLSI), as the Moore’s law is nearly to end, researchers are in search for alternative interconnect materials with excellent electrical and thermal conductivities. Various emerging reduced dimensional materials are under study to find an alternative to the Cu-based interconnect for post-CMOS technology nodes. In this regard, graphene (G) and carbon nanotubes (CNT) have been studied extensively in last decade. Since graphene and CNT have their own limitations in integrating with present CMOS technology, there is ongoing research to find hybrid materials, which can have simultaneously better thermal and electrical conductivity [1]. Recently, reduction in temperature has been observed in graphene encapsulated Cu wires [2] and potential application of graphene as a heat spreader. Since Cu-based VLSI interconnect is already in use in current CMOS technology it would be easier to integrate graphene as a Cu barrier layer and the heat spreader. Low-cost CVD techniques for large area graphene deposition on Cu film are well known. Graphene deposition on Cu includes an annealing process which eventually increases crystal integrity of Cu with larger grain size. In addition, graphene works as a barrier layer for Cu ion to diffuse into the dielectric. This is why G/Cu hybrid interconnect is a very good case for investigating electronic properties. Motivated by recent experiments, we have studied theoretically G/Cu structure in bulk and in one-dimension (1D) as next generation wire for nano-electronic applications. Our purpose is to investigate electronic properties of this structure with density functional theory (DFT). In this paper, we report density of states (DOS) and the quantum capacitance of (CQ) of G/Cu nanoribbon interconnect. We used DFT to study electronic band structure within Quantum-Espresso (QE) code. QE calculation is based on self–consistent plane-wave with Perdew-Zunger (PZ) pseudo-potential. We have considered one-dimensional slice of G/Cu interconnect of width 5nm, height 0.8nm and a variable length. A single layer of graphene is deposited on top of three atomic layers of Cu {111}. Cu {111} is chosen because this plane is closest to graphene lattice within 2% lattice mismatch. Among these three atomic layers, bottom two layers were fixed to their bulk lattice positions to represent bulk atoms. Top Cu layer and graphene layer were relaxed to find minimum force position. After obtaining atomic positions from relaxation calculations in QE, we performed self-consistent field calculation and band structure calculation. Details of DFT calculation is reported in our earlier work [3]. From electronic band structure, the electron density of states (DOS) is calculated. CQhas been calculated from DOS. C-V characteristics of a 5nm wide G/Cu nanoribbon interconnect (1D) is computed and also compared with G/Cu 2D case. For the purpose of comparison, we calculated quantum capacitance per unit area for both 1D and 2D cases. We have observed significant enhancement of CQ in G/Cu nanoribbon from its 2D counterpart. More electrons tunnel from underlying Cu substrate to graphene layer which cause more carrier density and enhances CQ. Dirac point shifting is also observed which is due to work function difference of G and Cu. Because of Dirac point shifting minimum capacitance point is also shifted from charge neutrality point. Near charge neutrality point, CQis nearly “V” shaped as in graphene but minimum capacitance is non-zero unlike graphene. This calculation is very useful in understanding electrical performances of G/Cu nanoribbon interconnect towards finding a suitable candidate of next generation interconnect materials. Due to enhanced capacitance, beside VLSI interconnect application, this work can be used for charge storage devices also. Acknowledgement:Part of this work is supported by the United States Air Force Research Laboratory under agreement number FA9453-10-1-0002. The U. S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon. Portions of this research were conducted with high performance computing resources provided by Louisiana State University (http://www.hpc.lsu.edu). [1] P. Goli, H. Ning, X. Li, C. Y. Lu, K. S. Novoselov, and A. A. Balandin, “Thermal Properties of Graphene–Copper–Graphene Heterogeneous Films,” Nano Letters,vol. 14, no. 3, pp. 1497-1503, April 12, 2014. [2] R. Mehta, S. Chugh, and Z. Chen, “Enhanced Electrical and Thermal Conduction in Graphene-Encapsulated Copper Nanowires,” Nano Letters,vol. 15, no. 3, pp. 2024-2030, March 11, 2015. [3] K. M. Mohsin, A. Srivastava, A. K. Sharma, C. Mayberry, and M. S. Fahad, “Current Transport in Graphene/Copper Hybrid Nano Ribbon Interconnect: A First Principle Study,” ECS Transactions, vol. 75, no. 13, pp. 49-53, August 25, 2016.

Electromagnetic simulation of VLSI circuits by the modified ADI‐FDTD method

ABSTRACTThe alternating direction implicit (ADI) finite‐difference time‐domain (FDTD) method can be used to simulate very large scale integration (VLSI) circuits efficiently as the time step is not restricted by the Courant–Friedrich–Levy stability condition. When the Berenger's split‐field perfectly matched layer (PML) absorbing boundary condition is used for the ADI‐FDTD method for open region simulation, the PML implementation will make this scheme unstable. In this article, the modified PML conductivity profiles are proposed to improve the stability of this scheme. Numerical simulations of the VLSI interconnect and RF inductor in time domain and frequency domain will be demonstrated to show the efficiency and accuracy of this method. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2530–2534, 2014

Performance and Analysis of Voltage Scaled Repeaters for Multi-Walled Carbon Nanotubes as VLSI Interconnects

Multi-walled carbon nanotubes (MWCNT) are promising candidates for futuristic Nano-electronic applications. MWCNT have potential to replace on-chip copper (Cu) interconnects due to their large conductivity and current carrying capabilities. Delay is one of the major design constraints in very large scale integration (VLSI) circuits. This paper presents an analysis of propagation delay and effect of repeater insertion on propagation delay for both MWCNT and Cu interconnects at different technology nodes viz 32nm and 22nm. In addition this paper deals with effect of voltage scaling in repeaters for long interconnects length in VLSI circuits in terms as propagation delay. It has been observed that propagation delay reduces with increase in bias voltage of the repeater at different interconnects length and technology nodes (32nm.22nm).

VLSI interconnects and their testing: prospects and challenges ahead

PurposeThe purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.Design/methodology/approachIn the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.FindingsThe effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.Originality/valueThis paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

Effects of process variation in VLSI interconnects – a technical review

PurposeProcess variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.Design/methodology/approachThe impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.FindingsParametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic.Originality/valueThis paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.

On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects

This paper presents a comprehensive study of the applicability of single-walled carbon nanotubes (SWCNTs) as interconnects in nanoscale integrated circuits. A detailed analysis of SWCNT interconnect resistance (considering its dependence on all physical parameters, as well as factors affecting the contact resistance), the first full 3-D capacitance simulations of SWCNT bundles for realistic very large scale integration (VLSI) interconnect dimensions, and a quantitative evaluation of the importance of inductive effects in SWCNT interconnects are presented. The applicability of carbon nanotube (CNT) based vias (vertical interconnects)-the most realizable CNT interconnects in the current state of the art-is addressed for the first time. It is shown that CNT interconnects can provide 30%-40% improvement in the delay of millimeter-long global interconnects. The applicability of CNT monolayers as local interconnects is found to be much more limited than that reported in the prior literature. Dense CNT bundle global interconnects are shown to offer a 4times reduction in power dissipation while achieving the same delay as optimally buffered Cu interconnects at the 22 nm node. This power saving increases to 8times at the 14 nm node. Furthermore, 3-D finite-element electrothermal simulations show that CNT bundles used as vias in between Cu metal layers can provide large improvement in metal interconnect lifetime by lowering the temperature of the hottest interconnects.

Expression of Concern: Understanding the Impact of Inductance in Carbon Nanotube Bundles for VLSI Interconnect Using Scalable Modeling Techniques

In this paper, we develop accurate and scalable models for the magnetic inductance in bundles of single-walled carbon nanotubes, which have been proposed as a means to alleviate the increasingly critical resistance problems associated with traditional copper interconnect in very large scale integration (VLSI) applications. The models consider the density and statistical distribution of both metallic and semiconducting nanotubes within the bundle. We evaluate the speed, accuracy, and scalability of our magnetic inductance modeling techniques and previously proposed inductance models. The inductance model with the best performance evaluates the magnetic inductance of nanotube bundles with excellent accuracy when compared to modeling each nanotube individually and provides orders of magnitude improvement in CPU time as the bundle size increases. Leveraging the magnetic inductance modeling techniques, we determine the relative impact of magnetic and kinetic inductance. Based on our results, the relative value of magnetic and kinetic inductance on single-walled carbon nanotube (SWCNT) bundles is highly dependent on the bundle geometry and the per unit length kinetic inductance

Repeater insertion in global interconnects in VLSI circuits

PurposeDelay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.Design/methodology/approachTrade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.FindingsOptimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage‐scaling. This leads to area and further power saving.Research limitationsThe bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.Originality/valueThe paper is of high significance in VLSI design and low‐power high‐speed applications. It is also valuable for new researchers in this emerging field.

Low-Frequency Noise Measurement-Based Reliability Testing of VLSI Interconnects with Different Geometry

Low-frequency noise measurements were performed on thin metallic very large-scale integration (VLSI) interconnects of three different geometries. These measurements were carried out under stressing current densities between 1.0/spl times/10/sup 5/ A/cm/sup 2/ and 2.2/spl times/10/sup 6/ A/cm/sup 2/ at different ambient temperatures up to 280/spl deg/C, in order to investigate the dependence of low-frequency noise on the geometrical shape of the VLSI interconnects. The behavior of these samples under these conditions is analyzed in this letter.

A novel dimension-reduction technique for the capacitance extraction of 3-D VLSI interconnects

In this paper, a new capacitance extraction method called the dimension-reduction technique (DRT) is presented for three-dimensional (3-D) very large-scale integration (VLSI) interconnects. The DRT converts a complex 3-D problem into a series of cascading simple two-dimensional (2-D) problems. Each 2-D problem is solved separately, thus we can choose the most efficient method according to the arrangement of conductors. We have used the DRT to extract the capacitance matrix of multilayered and multiconductor crossovers, bends, vias with signal lines, and open-end. The results are in close agreement with those of Ansoft's SPICELINK and the Massachusetts Institute of Technology's (MIT) FastCap, but the computing time and memory size used by the DRT are several (even ten) times less than those used by SPICELINK and FastCap.

Simulation of Microstructure and Surface Profiles of Thin Films for VLSI Metallization

A crucial step in the manufacture of very large-scale integration (VLSI) integrated circuits is the fabrication of reliable, low-resistance metal interconnects between semiconductor devices. The fabrication of these interconnects is generally performed by depositing a blanket metal film and then patterning it by lithographic and etching techniques. The primary means of depositing thin metal films for VLSI interconnects are sputtering and chemical vapor deposition (CVD).The creation of reliable interconnects is, however, complicated by a number of issues. In order to obtain low contact resistance, to inhibit reactions with the silicon, and to provide good adhesion to both Si and SiO2, contact, barrier, and adhesion layers are generally deposited prior to the deposition of the low-resistance metal film that forms the bulk of the interconnect. If these layers are to provide an effective barrier to diffusion of the interconnection metal to the silicon, they must be deposited in a uniform, homogeneous form. It is also necessary that the primary interconnect material have as high step coverage as is possible in order to reduce current crowding, local heating effects, and electromigration. Unfortunately, as VLSI circuit densities have increased, the fabrication of interconnects requires high aspect-ratio contact cuts, and relatively severe local topographies can result. These factors make it difficult to deposit films with good step and bottom coverage.In addition to these concerns with the film surface profile, another factor is becoming increasingly significant. Both sputtering and CVD produce thin films with characteristic microstructures. This microstructure consists of columns or grains separated by grain boundaries and voids.