Vertical Thin Film Transistor Research Articles

P‐17: Development of Vertical Oxide Channel Thin Film Transistor Based on Hard‐Mask Etching

Avertical oxide semiconductor thin film transistor (VTFT) with channel lengthof 0.4 μm wasdeveloped in our work. This VTFT has a small footprint, which isconducive to achieving higher resolutiom. In this work, we produced a VTFT by usinga hardmask etching process and designed different vertical structures, such asslope, hole, etc. The device achieved an on‐state current of 20.6 μA (normalized with width) and an off‐state current below 1 pA.

Four-terminal polycrystalline-silicon vertical thin-film transistors on glass substrates

This study aimed to fabricate n-channel four-terminal (4 T) polycrystalline silicon (poly-Si) vertical thin-film transistors (VTFTs) with submicron gate lengths on a glass substrate. The 4 T VTFTs have a poly-Si active layer crystallized via metal-induced crystallization using nickel (Ni-MIC), a top gate (TG), and a bottom gate (BG). Here, the TG covers all the channel regions, and the BG affects only a part of the channel region. A double-gate drive (simultaneous operation of both gates) displayed a high I on/I off ratio and small s.s. compared with those of a single-gate drive. In addition, the threshold voltage (V th) of the TG drive varied depending on the BG voltages (V BG), with a γ-value (=ΔV th/ΔV BG) of 0.17. This value is smaller than the theoretically expected value because of the localized effects of the BG on the channel region and the inferior crystalline quality of the Ni-MIC poly-Si film.

Scaling Benefits for Active and Gate Insulator of Vertical Channel Thin-Film Transistors Using Atomic Layer Deposited InGaZnO Channel

Scaling Benefits for Active and Gate Insulator of Vertical Channel Thin-Film Transistors Using Atomic Layer Deposited InGaZnO Channel

High-k dielectric based high performance vertical organic thin film transistor for flexible low power applications

The basic performance parameters such as threshold voltage, drain current and saturation mobility play an important role for any transistor-based devices. The planar organic TFT provides a good performance but it is still not satisfactory. Therefore, in this paper, a vertical channel TFT (D5) is proposed that exhibits a significant improvement for threshold voltage V t , drain current I Dmax and saturation mobility μ sat in comparison to planar devices. The proposed vertical device (D5) is 44 and 24 times enhanced in comparison with planar device D1 in terms of I Dmax and μ sat , correspondingly. Furthermore, this paper compares five different vertical-channel device architectures (D2, D3, D4, D5, D6 & D7). Out of these structures, our proposed novel structure (D5) shows remarkable performance in terms of drain current (528 μA) and saturation mobility (80.8 cm2/V.s). As compared to the best mentioned vertical devices D2, D3 and D7, the proposed device exhibits 41.8 %, 15.6 % and 27.8 %, increment in drain current, respectively. Additionally, the proposed device exhibits about 2.7, 5.2 and 3.5 times improvement in comparison with D2, D3 and D7 correspondingly. The reasons for this better performance of the proposed device have been explained by vertical and horizontal cutline analysis.

Impact of Al2O3 spacers on the improvement in short-channel effects for the mesa-shaped vertical-channel In-Ga-Zn-O thin-film transistors with a channel length below 100 nm

To achieve a channel length scaling and an improvement in short-channel effect (SCE) for the mesa-shaped vertical thin-film transistors (VTFTs) using In-Ga-Zn-O (IGZO) channels prepared by atomic layer deposition (ALD), the impacts of two strategic approaches were investigated: the introduction of an ALD Al2O3 spacer and the modulation of ALD oxidants. The Al2O3 spacers were patterned with sound profiles by means of a hybrid-etching technique combining a wet- and plasma dry-etching processes to form vertical sidewalls corresponding to a channel length. For the cases when the Al2O3 spacers were prepared with H2O oxidant, the IGZO VTFT with an In/Ga ratio of 1.7 showed the degradations in device characteristics including a turn-on voltage (VON) of −8.0 V and a subthreshold swing (SS) of 1.50 V/dec. When the In/Ga ratio was increased to 2.9, the device failed to be operated with conductive properties. The excess hydrogen contained within the Al2O3 spacer was suggested to be thermally diffused into the IGZO from the back-channel interface, leading to marked increase in the number of conduction carriers within the channel. To suppress the doping effect of hydrogen from the spacer, the ALD oxidant was strategically modulated to O3. As results, the VON and SS of the IGZO VTFT were markedly improved to be −2.0 V and 0.483 V/dec, respectively. Additionally, the drain induced barrier lowering coefficient was also significantly enhanced from 2.9 to 0.13 V/V, demonstrating the excellent immunity against the SCE for the IGZO VTFTs with nanoscale channel lengths. It was concluded from these findings that the spacer engineering can be one of the most important guides for the implementation of IGZO VTFTs with channel lengths below 100 nm.

Ultra-thin vertical tft photosensor and photosynapse based on au-doped- graphene under transition metal selenide reaction

The development of artificial photosensitive synapses with high sensitivity and biomimetic properties that combine innovative concepts and neuromorphic architectures is crucial to achieving highly integrated and flexible intelligent visual systems. Recently, graphene heterostructure-based photosensitive synaptic transistors have been extensively studied for this purpose. However, compared to traditional transistors, vertical structure thin film transistors (VTFTs) with ultra-short channels and advantages, such as high integration, have yet to be investigated in photosensitive synapses. Here, we report an ultra-thin VTFT featuring a graphene/WxSex–1 van der Waals heterostructure that combines photonic and neuromorphic elements. We demonstrate a VTFT in which the channel layer is formed by covalently bonded WxSex–1 nanomaterials produced by introducing Se atoms on the surface of a tungsten metal thin film deposited via radio-frequency sputtering. This structure successfully simulated the main synaptic function, exhibited photosensitive synaptic responses to ultraviolet (λ = 365 nm) light, and demonstrated highly reliable electrical performance. Furthermore, the incorporation of gold nanoparticles changed the photosensitive synaptic response properties of the graphene/WxSex–1 heterostructure from excitatory to inhibitory, showing a responsivity of about ∼14 A W–1, which was attributed to the heterojunction interface resonant effects and efficient charge transfer induced by localized surface plasmons. This further enabled optical artificial synaptic applications while operating with low voltage spikes and low light intensity. This work provides a novel strategy for integrating and developing biological and nano-electronic systems.

Improvement in Short-Channel Effects and Bias-Stress Stability of Vertical Thin-Film Transistors Using Atomic-Layer-Deposited In–Ga–Sn–O Channels

Improvement in Short-Channel Effects and Bias-Stress Stability of Vertical Thin-Film Transistors Using Atomic-Layer-Deposited In–Ga–Sn–O Channels

Characteristics of Ultrathin Indium Oxide Thin‐Film Transistors with Diverse Channel Lengths Fabricated by Atomic Layer Deposition

The oxide thin‐film transistors (TFTs) with ultrathin (5 nm) crystalline In2O3 channels formed by an atomic layer deposition method are fabricated. The ultrathin In2O3 films are formed at a deposition temperature of 300 °C using (3‐(dimethylamino)propyl)dimethylindium as the indium precursor and ozone as the oxidizing agent. The postannealing is performed in an oxygen atmosphere for 2 h at 300 °C. The scaling behavior of the field‐effect mobility (μFE) is investigated as a function of the channel length (Lch). As Lch increases from 5 to 160 μm, the average μFE is measured and found to increase from 20.2 to 33.6 cm2 V−1 s−1. It shows the average device properties of subthreshold swing of 0.32 V dec−1, turn‐on voltage of −5.5 V, and on/off current ratio of 107. To understand this trend, the transmission line model is utilized to extract the resistance components present across the channel quantitatively. The analyses reveal that among the components comprising the total resistance, the fraction of Rc increases as Lch becomes shorter. Thus, Rc emerges as a dominant parameter that determines μFE. In this regard, the results have technical significance in vertical TFTs and high‐resolution applications in which predictable scaling matters.

Effect of source–drain contact and channel length on the performance of vertical thin-film transistors

Vertical thin-film transistors (V-TFTs) with an InSnO-stabilized ZnO channel were fabricated. The vertical architecture enables devices with submicron channel lengths (≤500 nm) to afford delivering drain current greatly exceeding that of conventional planar TFTs. Due to the submicron length of the V-TFT channel, an on/off state current higher than 107 can be achieved even with a drain voltage of 0.01 V, and the subthreshold swing was kept in the tens of mV/dec range owing to the efficacious device preparation. In order to understand the influence of structures on the device performance, the source–drain (S/D) contact and the channel length of V-TFTs were designed and studied. The results show that the increase in the contact area between the active layer and the S/D region can reduce the S/D contact resistance, thus affecting the drain current across the threshold region. When the channel length is shortened to a deep submicron size, the electrostatic coupling between the source and drain electrodes will lead to a decrease in the S/D barrier. This leads to the leakage-induced barrier reduction effect of V-TFTs.

Research Progress of Vertical Channel Thin Film Transistor Device.

Thin film transistors (TFTs) as the core devices for displays, are widely used in various fields including ultra-high-resolution displays, flexible displays, wearable electronic skins and memory devices, especially in terms of sensors. TFTs have now started to move towards miniaturization. Similarly to MOSFETs problem, traditional planar structure TFTs have difficulty in reducing the channel's length sub-1μm under the existing photolithography technology. Vertical channel thin film transistors (V-TFTs) are proposed. It is an effective solution to overcome the miniaturization limit of traditional planar TFTs. So, we summarize the different aspects of VTFTs. Firstly, this paper introduces the structure types, key parameters, and the impact of different preparation methods in devices of V-TFTs. Secondly, an overview of the research progress of V-TFTs' active layer materials in recent years, the characteristics of V-TFTs and their application in examples has proved the enormous application potential of V-TFT in sensing. Finally, in addition to the advantages of V-TFTs, the current technical challenge and their potential solutions are put forward, and the future development trend of this new structure of V-TFTs is proposed.

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In–Ga–Zn–O bilayer channel configuration

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs. Here we show a novel strategy to introduce an In–Ga–Zn–O (IGZO) bilayer channel configuration, which was prepared by atomic-layer deposition (ALD), in terms of structural and electrical passivation against the back-channel effects. Two-dimensional electron gas was effectively employed for improving the operational reliability of the VTFTs by inducing strong confinement of conduction electrons at heterojunction interfaces. The IGZO bilayer channel structure was composed of 3 nm-thick In-rich prompt (In/Ga = 4.1) and 12 nm-thick prime (In/Ga = 0.7) layers. The VTFTs using bilayer IGZO channel showed high on/off ratio (4.8 × 109), low SS value (180 mV dec−1), and high current drivability (13.6 μA μm−1). Interestingly, the strategic employment of bilayer channel configurations has secured excellent device operational stability representing the immunity against the bias-dependent hysteretic drain current and the threshold voltage instability of the fabricated VTFTs. Moreover, the threshold voltage shifts of the VTFTs could be suppressed from +5.3 to +2.6 V under a gate bias stress of +3 MV cm−1 for 104 s at 60 °C, when the single layer channel was replaced with the bilayer channel. As a result, ALD IGZO bilayer configuration could be suggested as a useful strategy to improve the device characteristics and operational reliability of VTFTs.

Contact properties of a low-resistance aluminum-based electrode with metal capping layers in vertical oxide thin-film transistors

Vertical thin-film transistors (TFTs) with low contact resistance are necessary to realize high-resolution displays for virtual reality and augmented reality applications.

Preparation and analysis of single and hybrid metal-phthalocyanine organic phototransistors and comparison of their photoelectric properties

Vertical organic thin film transistors (VOTFT) in a five-layer structure of ITO/MPc/Al/MPc/Cu were prepared using a single phthalocyanine or two hybrid phthalocyanine material co-blended films as the active layer. The prepared single phthalocyanine device and the mixed phthalocyanine material device experimented with static operating characteristics. The threshold voltage of the device of ZnPc is 1 V, while the threshold voltage of the hybrid material is reduced, and the threshold voltage of the device of CuPc mixed with ZnPc can reach 0.4 V. The results of the photoelectric characteristics of the devices show that the light sensitivity of the hybrid material is significantly better than that of the single material. The light sensitivity of the 1:1 blend of PbPc mixed with ZnPc device has the greatest photosensitivity, 5.37 times that of ZnPc and 141.62 times that of PbPc. The device switching parameters for the hybrid materials are ton = 0.4 ms and toff = 0.44 ms, which switching characteristic times in the sub-millisecond range. The cut-off frequency of the hybrid materials has also increased, with the highest mobility VOTFT of ZnPc mixed with PbPc reaching a cut-off frequency of 4.6 kHz.

전기화학적으로 산화된 투과성 베이스 전극을 갖는 수직구조 유기 트랜지스터

Vertical organic thin film transistors (VOTFTs) are emerging electronic devices that can overcome the limitations of conventional organic thin film transistors (OTFTs) based on lateral architecture. Here, organic permeable base transistors (OPBTs) are formed with an oxide layer on the base electrode through an electrochemical process called anodization, and this oxide layer acts as a dielectric layer. Through this electrochemical method, the manufacturing process is simplified and the charge carrier transport of the VOTFT is improved. In this study, the thickness of AlOx formed by anodizing the Al electrode was calculated through the capacitance-voltage measurement of the metal-insulator-metal device, and OPBT operations were observed according to the anodizing potential and interfacial layer, respectively. In addition, we observed the specific behaviors of vertical OPBT depending on the applied potential correlations between middle base electrode and bottom collector electrode.

Geometrical and Structural Design Schemes for Trench-Shaped Vertical Channel Transistors Using Atomic-Layer Deposited In-Ga-Zn-O

Trench-structured In-Ga-Zn-O vertical thin-film transistors (T-VTFT) was fabricated with a channel length of 400 nm. T-VTFTs showed channel width-dependent field-effect mobility owing to the back-channel scattering, and the mobility of 24.1 cm2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$/$ </tex-math></inline-formula> Vs was finally obtained with a channel width of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 ~\mu \text{m}$ </tex-math></inline-formula> . Alternatively, the asymmetric operations of conventional mesa-shaped VTFTs were improved in a symmetrical way owing to the structural benefits of the T-VTFT, leading to excellent immunity against the drain-induced barrier lowering.

Elucidation of electric characteristics for P and N type polycrystalline silicon vertical thin film transistors

P and N type polycrystalline silicon has been applied in thin film transistors (TFTs) for driving a range of displays, and for building up complementary metal oxide semiconductor (CMOS)-like circuits. In one aspect, the high driving current is required, which is usually achieved by improving field effect mobility of the active layer. For another, balanced electrical characteristics are required for achieving CMOS-like logic circuits. In this article, in order to increase driving current, P and N type polycrystalline silicon vertical TFTs configuration is proposed that can get rid of the strict requirement of the field effect mobility in order to increase the driving current. In addition, the balanced electrical properties are demonstrated for P and N type vertical TFTs, which are elucidated by the density of states calculations. The simple Simulation Program with Integrated Circuit Emphasis (SPICE) modelling indicates the potential application in CMOS inverter based on our vertical TFTs.

Modeling of High-Current Polycrystalline Silicon Thin Film Transistors by Incorporating Buried Electrode

For display applications, high current and large on/off current ratio are pursued for driving and switching transistors. In this article, a thin film transistor (TFT) device incorporating a buried electrode is proposed, which enables increasing the driving current by reducing the channel length, with the channel length only at the drain side. This lateral short-channel TFT enables increasing the on-current while maintaining the field effect mobility, in comparison to our experimental short-channel vertical TFT structure. Another advantage of the proposed structure lies in the suppression of the Schottky barrier at the source and drain contacts when using high-work-function source/drain contacts for an N-type TFT, with an increased on/off current ratio reaching approximately 106. The suppression of Schottky barrier at the source/drain has been verified by the contact resistance measurements. Even though high driving current is obtained, the off-current is still high due to the weakened electric field at the source/drain sides and needs to be further optimized.

Vertical ferroelectric thin-film transistor array with a 10-nm gate length for high-density three-dimensional memory applications

Hafnia-based ferroelectric thin-film transistors (FeTFTs) are regarded as promising candidates for future nonvolatile memory devices owing to their low power consumption, high operational speed, and complementary metal–oxide–semiconductor compatibility. However, the scalability of hafnia-based materials and the feasibility of three-dimensional (3D) device fabrication should be confirmed for ultrahigh-density memory applications. In this work, we demonstrate that FeTFTs can be scaled down to a 10-nm dimension using the vertical structure with a hafnia-based ferroelectric gate insulating layer and an oxide semiconductor channel. We show that such vertical FeTFTs can be operated with an effective device size of 0.005 μm2, a fast operation speed of &amp;lt;100 ns, and a high endurance of 108 cycles. Additionally, the string-level NAND operation is demonstrated using the vertical FeTFT array. Finally, device simulation confirms the possibility of ultrahigh-density 3D ferroelectric NAND with 200 gate stacks. These results demonstrate the ultrahigh scalability of FeTFTs as a promising candidate for next-generation 3D nonvolatile memory.

Elucidation of the Density of States for Polycrystalline Silicon Vertical Thin-Film Transistors

The polycrystalline silicon vertical thin-film transistors (TFTs) with different active layer thicknesses of 150 and 300 nm were fabricated by a five-mask process and electrically characterized. The vertical TFT with 150-nm active layer thickness shows comprehensive advantages over its counterpart with 300-nm active layer, especially with a higher ON/OFF current ratio <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ </tex-math></inline-formula> of more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> and higher field-effect mobility, excluding the access resistance effect. The electrical parameters were analyzed by the density of states (DOS) calculation, and smaller DOS is deduced for the device with 150-nm active layer for the same energy level. The detailed elucidation of the DOS was analyzed by introducing the intrinsic mobility and the grain boundary barrier height at the flat-band state, which gives the detailed expressions for the DOS. Polycrystalline silicon lateral TFT was also introduced to verify this evaluation method.

Vertical oxide thin-film transistor with interfacial oxidation

A vertical oxide thin-film transistor was developed with interfacial oxidation for low voltage operation. The gate metal was used as a spacer for the definition of the transistor’s channel as well as the gate electrode. After definition of the vertical side wall, an IGZO (In-Ga-Zn Oxide) layer was deposited, followed by the interfacial oxidation to form a thin gate insulator. Ta was used for the gate material due to the low Gibbs free energy and high dielectric constant of tantalum oxide. A 15 nm tantalum oxide layer was obtained by the interfacial oxidation of Ta at 400 °C under oxygen atmosphere. The thin gate oxide made it possible to operate the transistor under 1 V. The low operation voltage enables low power consumption, which is essential for mobile application.