Vertical Slit Field Effect Transistor Research Articles

Analytical Modeling of Surface Potential and Threshold Voltage for Junctionless Double Gate Vertical Slit Field Effect Transistor

Analytical Modeling of Surface Potential and Threshold Voltage for Junctionless Double Gate Vertical Slit Field Effect Transistor

A 2D Potential Based Threshold Voltage Model Analysis and Comparison of Junctionless Symmetric Double Gate Vertical Slit Field Effect Transistor

ABSTRACT In the present paper, a two-dimensional (2D) potential-based analytical model of threshold voltage for junctionless symmetric double gate vertical slit field effect transistor (JL SDG VeSFET) is developed. The proposed model is based upon the solution of 2D Poisson's equation and is also extended to consider the effect of third dimension on threshold voltage of the device. The model includes the effect of various device parameters such as geometric gate length, dielectric thickness, substrate doping, and metal gate work function on threshold voltage, and is compared with conventional metal oxide semiconductor field effect transistor (MOSFET) device in order to show better performance of junctionless transistor and its application for future low power very large scale integration (VLSI) circuits. The analytical model is assessed with 2D TCAD Sentaurus simulation. The analytical model not only provides useful physical insight into the subthreshold behavior of the device, but also offers basic design guideline to better exploit its scaling potential for future nanoscale devices. It has been reported that the proposed model is in good agreement with simulative analysis with only a marginal deviation of about 3% for various device parameters.

Analytical Modeling of Drain Current and Short Channel Effects of Junctionless Double Gate Vertical Slit Field Effect Transistor

Analytical Modeling of Drain Current and Short Channel Effects of Junctionless Double Gate Vertical Slit Field Effect Transistor

Performance analysis of junctionless double gate VeSFET considering the effects of thermal variation – An explicit 2D analytical model

The purpose of this paper is to explore junctionless double gate vertical slit field effect transistor (JLDG VeSFET) with reduced short channel effects and to develop an analytical threshold voltage model for the device considering the impact of thermal variations for the very first time. The model has been derived by solving 2D Poisson’s equation and the effects of variation in temperature on various electrical parameters of the device such as Rout, drain current, mobility, subthreshold slope and DIBL has been studied and described in the paper. The model provides a deep physical insight of the device behavior and is also very helpful in contributing to the design space exploration for JLDG VeSFET. The proposed model is verified with simulative analysis at different radii of the device and it has been observed that there is a good agreement between the analytical model and simulation results.

Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips

Thermal management becomes a huge challenge for modern IC designers, especially when chips go 3-D. Vertical slit field-effect transistor (VeSFET) technology provides an alternative thermal-friendly design choice. VeSFET-based chips not only have a much lower power density but also a better vertical thermal conductivity than their CMOS counterparts. For a VeSFET chip with ten stacked dies, the temperature increase is only 30% of that for CMOS-based chip. Assuming the same scaling trend for CMOS and VeSFET, VeSFET 3-D chips can postpone the appearance of dark silicon by three technology nodes compared with CMOS implementations. For VeSFET-based designs, different topologies of transistor arrays may result in different thermal behaviors. We perform thermal characterization of two-transistor array topologies.

Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure

In this paper, we demonstrate that standard cell design methodology can be applied to design vertical slit field effect transistor (VeSFET)-based ASICs with modern CMOS EDA tools. We study a family of VeSFET canvases-chain canvases that improve performance and power consumption of circuits mapped to them compared to circuits implemented with VeSFET canvases composed of isolated transistors. We compare the designs implemented with a commercial low power CMOS library and corresponding VeSFET libraries. VeSFET-based designs demonstrate significant power reduction as compared to the CMOS-based designs at the same performance.

Routing Challenges for Designs With Super High Pin Density

Footprint scaling may reduce wire lengths when more metal layers are available for routing. To achieve optimal wire length, footprint should be very small in which case pin density will be extremely high. However, high pin density may lead to detailed routing failure. We demonstrate that there is a threshold pin density beyond which standard routing heuristics fail to access pins on the bottom layer, even with unlimited number of metal layers available for routing. Future technologies, such as vertical slit field-effect transistor (VeSFET), may have layouts with pin density exceeding the threshold. We show that VeSFET layouts are still routable within footprint using two-sided routing. Compared to one-sided routing, two-sided routing achieves shorter wire lengths and fewer vias, hence lower interconnect capacitance and better performance.

Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current (<; 5 pA/μm) and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio (>; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> ). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

Circuit design with adjustable threshold using the independently controlled double gate feature of the Vertical Slit Field Effect Transistor (VESFET)

Abstract. The recently introduced Vertical Slit Field Effect Transistor allows for adjusting its threshold voltage through independent controllable gates. This feature can be applied to a broad range of circuits. In this paper two examples are presented. First, a ring oscillator with a wide frequency tuning range and second, a Schmitt trigger with a controllable hysteresis.

Circuit design with Independent Double Gate Transistors

Abstract. Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. This paper introduces a novel Vertical Slit Field Effect Transistor with unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits. A new adder circuit is proposed, where the power could be reduced by one fifth and the area by on third compared to a tied gate configuration.