Abstract
Thermal management becomes a huge challenge for modern IC designers, especially when chips go 3-D. Vertical slit field-effect transistor (VeSFET) technology provides an alternative thermal-friendly design choice. VeSFET-based chips not only have a much lower power density but also a better vertical thermal conductivity than their CMOS counterparts. For a VeSFET chip with ten stacked dies, the temperature increase is only 30% of that for CMOS-based chip. Assuming the same scaling trend for CMOS and VeSFET, VeSFET 3-D chips can postpone the appearance of dark silicon by three technology nodes compared with CMOS implementations. For VeSFET-based designs, different topologies of transistor arrays may result in different thermal behaviors. We perform thermal characterization of two-transistor array topologies.
Published Version
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