Vertical Metal-oxide-semiconductor Field-effect Transistors Research Articles

Lowering of Schottky Barrier Height in a Vertical Pillar MOSFET by Deuterium Annealing

The Schottky barrier height (Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> ) is lowered by high-pressure deuterium annealing (HPDA), in a vertical pillar (VP) metal-oxide-semiconductor field effect transistor (MOSFET). Typical device characteristics were comparatively studied before and after HPDA. A change of contact resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ) at a Schottky junction was also analyzed by using a transmission line method (TLM). Moreover, HPDA effects on the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> were characterized on different crystal orientations of silicon, which has a different number of traps. HPDA is more effective to lower the Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> at (111) orientation than at (100) orientation because a greater number of interface traps can be passivated for an orientation with a high Miller index. Finally, a deuterium peak was physically profiled across the Schottky junction by use of time-of-flight secondary ion mass spectrometry (ToF-SIMS).

650V Vertical SiC MOSFETs and Diodes with Improved Terrestrial-Neutron Single-Event Burnout

Silicon carbide (SiC) power devices such as Schottky diodes and metal-oxide semiconductor field-effect transistors (MOSFETs) are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state. In this study the effects of the drift layer design of 650V SiC vertical power diodes and MOSFETs have been studied. TCAD simulations of different device designs have been performed, and fabricated device single-event burnout (SEB) properties are compared between the devices fabricated. We find that the standard 650V devices have a low area-scaled failure-in-time (FIT/cm2) such that essentially no failures (0.01 FIT/cm2) are expected at 400V drain-source bias (VDS) operation and below. An improved design allows the SEB failure rate curve to be shifted downward in failure rate, such that at for a given VDS operation condition, the FIT/cm2 can be decreased by 10 - 100 times, depending on the VDS value. This allows operation at about 75V higher VDS value with a similar SEB failure rate, allowing these devices to be used in a wider range of applications.

Normally-off operation in vertical diamond MOSFETs using an oxidized Si-terminated diamond channel

We fabricated (001) vertical diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with oxidized Si-terminated (C–Si–O) diamond channels on the surfaces and trench sidewalls. The C–Si–O diamond surface is approximately 1.0 eV weaker in negative electron affinity than the hydrogen-terminated (C–H) diamond surface, resulting in a smaller valence band bending between the interface of C–Si–O diamond surface and Al2O3, and larger the difference between the energy values of the fermi level and the valence band on the top (EF−EV), and the threshold voltage (Vth) shifts in the negative direction. As a result, the maximum drain current density was 108 mA/mm, the Vth was −9.0 V. Compared with conventional vertical diamond FETs using a C–H channel, the Vth was shifted more than 20 V in the negative direction to reach normally-off mode. The normally-off operation was achieved while maintaining high current density, which is the first case of normally-off operation that has been observed in vertical diamond FETs. In, addition, it was confirmed that the diode functions as a freewheeling diode by adding a reverse drain voltage and allowing current to flow, and the change of current-voltage characteristics was also investigated by swapping the source and drain positions and performing measurements.

Dependence of reverse leakage on the edge termination process in vertical GaN power device

The trench gate metal oxide semiconductor field effect transistor (MOSFET) represents a prominent device architecture among the Gallium Nitride (GaN) based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state that is related to the lateral edge termination is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

Enhancement-mode β-Ga2O3 U-shaped gate trench vertical MOSFET realized by oxygen annealing

Vertical metal–oxide–semiconductor field effect transistor (MOSFET) is essential to the future application of ultrawide bandgap β-Ga2O3. In this work, we demonstrated an enhancement-mode β-Ga2O3 U-shaped gate trench vertical metal–oxide–semiconductor field effect transistor (UMOSFET) featuring a current blocking layer (CBL). The CBL was realized by high-temperature annealing under oxygen ambient, which provided electrical isolation between the source and drain electrodes. The CBL thicknesses of different annealing temperatures were derived from C–V measurements and the Fermi level position of the sample surfaces of different annealing temperature was characterized by x-ray photoelectron spectroscopy measurements, indicating good process controllability. Furthermore, photoluminescence spectra were measured to study the effect of oxygen annealing. The fabricated UMOSFET showed normally off with a Vth of 11.5 V, an on-state resistance of 1.48 Ω cm2, a maximum on-state current of 11 A/cm2, an on–off ratio of 6 × 104, and a three-terminal breakdown voltage over 100 V. This work paves a way to form a CBL and broadens the design space for high-power β-Ga2O3 vertical transistors.

Charge deposition analysis of heavy-ion-induced single-event burnout in low-voltage power VDMOSFET

The heavy-ion-induced single-event burnout (SEB) risk in power MOSFETs (metal-oxide-semiconductor field-effect transistors) can be assessed in ground facilities, although it is costly and time-demanding. For this reason, there have been few experimental studies dedicated to investigate the relevant parameter related to the description of ion-induced SEB phenomenon. In this work the heavy-ion-induced SEB in a low-voltage power VDMOSFET (vertical double-diffused MOSFET) is studied using several ion-energy combinations. A self-consistent statistical analysis is carried out in order to elucidate the relationship between charge deposition and SEB triggering. Experimental data is compared to a predictive model from the literature for SEE (single-event effect) worst-case prediction in power MOSFETs, supporting for the first time its relevance to the worst-case prediction in the SEB mechanism.

Enhancement-Mode Heterojunction Vertical β-Ga2O3 MOSFET with a P-Type Oxide Current-Blocking Layer

The vertical heterojunction Ga2O3 MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with the p-type oxide as the current-blocking layer (CBL) is investigated for the first time using SILVACO simulation software. The results show that the threshold voltage of the device is easily positive, which means that the device works in the enhancement mode. By adjusting the doping concentration (from 2 × 1017 cm−3 to 2 × 1018 cm−3) and thickness (from 0.4 um to 2 um) of p-SnO CBL, the threshold voltage is around from 2.4 V to 2.8 V and the breakdown voltage of the device can be increased from 361 V to 518 V. Compared with the original homojunction Ga2O3 vertical MOSFET with CBL, the p-SnO CBL can greatly improve the performance of the device. Other p-type oxides are also investigated as the CBL and show promising performances. This work has a certain guiding significance for the design of a vertical enhanced current-blocking layer MOSFET device and for the development of a Ga2O3 heterojunction power device.

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si.

Sb-based semiconductors are critical p-channel materials for III–V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III–V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III–V CMOS technologies.

Electrical Performances of GaN-based Vertical Trench MOSFETs with Cylindrical and Hexagonal Structure

In this paper, we designed and analyzed the electrical performances of gallium-nitride (GaN)-based vertical trench metal-oxide-semiconductor field-effect-transistors (MOSFETs) using three-dimensional technical computer-aided design (3-D TCAD) simulation. The cylindrical device is generally considered as superior device than the polygonal devices because it has better gate controllability. In the case of GaN-based vertical devices, however, the cylindrical device performs inferiorly to the hexagonal device in terms of crystal directions for the GaN sidewall plane such as m-plane (1-100), a-plane (11-20), and c-plane (0001). The simulation results provide an understanding and design guidelines for which electrical properties of trench FETs are affected by cross-section shape.

Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance.

Thin vertical nanowires based on III–V compound semiconductors are viable candidates as channel material in metal oxide semiconductor field effect transistors (MOSFETs) due to attractive carrier transport properties. However, for improved performance in terms of current density as well as contact resistance, adequate characterization techniques for resolving doping distribution within thin vertical nanowires are required. We present a novel method of axially probing the doping profile by systematically changing the gate position, at a constant gate length Lg of 50 nm and a channel diameter of 12 nm, along a vertical nanowire MOSFET and utilizing the variations in threshold voltage VT shift (∼100 mV). The method is further validated using the well-established technique of electron holography to verify the presence of the doping profile. Combined, device and material characterizations allow us to in-depth study the origin of the threshold voltage variability typically present for metal organic chemical vapor deposition (MOCVD)-grown III–V nanowire devices.

(Invited) Development of Vertical Gallium Nitride Power Devices for Use in Electric Vehicle Drivetrains

The rapid acceleration of vehicle drivetrain electrification is expected to be a major driver for the widespread adoption of silicon carbide (SiC) power devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and junction-barrier-Schottky (JBS) diodes (the latter needed as the freewheeling diode in parallel with the MOSFET switch), due to their ability to increase the efficiency and reduce the volume of the power electronic inverter that ties the vehicle’s battery to the electric motor(s). The move from traditional silicon-based power electronics to SiC-based power electronics is necessary to achieve the U.S. Department of Energy (DOE) power electronics density target of 100 kW/L. However, gallium nitride (GaN)-based inverters may offer additional benefits beyond what can be achieved with SiC. For example, genetic-algorithm-based system-level simulations of the Pareto front trade-off between power density and efficiency of the inverter indicate that GaN power devices offer solutions superior to those achievable with SiC. However, given that the drivetrain DC bus voltage in future electric vehicles is expected to be 800 V or higher, commercially-available GaN power switching high electron mobility transistors (HEMTs), which typically have voltage ratings of 650 V or less, are unsuitable for a two-level inverter design, which is preferred by automotive system designers due to its simplicity and associated reliability. As such, vertical GaN power devices with voltage ratings of 1.2 kV or greater are necessary. This talk will describe our team’s efforts to develop both vertical GaN MOSFETs and JBS diodes. Designs for both trench MOSFETs and double-well MOSFETs (DMOSFETs) will be discussed. Experimental work has focused on trench MOSFETs, chiefly due to the need for selective-area doping in the DMOSFET, which is generally challenging in GaN and is particularly so in this structure due to the double well. The trench MOSFET presents significant challenges as well, including the need for a high-quality gate dielectric on the etched sidewall of the trench as well as mitigation of high electric fields at the bottom of the trench. Vertical GaN trench MOSFETs utilizing drift layers grown by metal-organic chemical vapor deposition (MOCVD) on native GaN substrates have been fabricated. Devices with an atomic-layer-deposited SiO2 gate dielectric have demonstrated a positive threshold voltage of ~8 V, an on/off ratio of ~108, and a current density of ~400 mA/mm. Additionally, GaN JBS diodes are being developed concurrently, and in this case selective-area doping cannot be avoided as alternating regions of p- and n-doped material are inherent to the operation of the device. Our team has utilized an etch-and-regrowth approach to demonstrate vertical GaN JBS diodes with reverse hold-off voltage >1.5 kV and forward turn-on voltage <1 V, consistent with JBS operation, although the reverse leakage current is higher than is typically observed for a continuously-grown GaN PN junction. Prospects to further improve device performance will be discussed, including reducing the reverse leakage current though advances in the selective-area p-GaN regrowth process. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office and by the ARPA-E PNDIODES program directed by Isik Kizilyalli. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

Novel Vertical Power MOSFET With Step Hk Insulator Close to Super Junction Limit Relationship Between Breakdown Voltage and Specific ON-Resistance by Improving Electric Field Modulation

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> (Hk) MOSFET concept in this article with the step high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42~\mu \text{m}$ </tex-math></inline-formula> . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

Study on a novel vertical enhancement-mode Ga 2 O 3 MOSFET with FINFET structure

A novel enhanced mode (E-mode) Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET) with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated. It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics. The metal material of the gate, the oxide material, the oxide thickness, and the epitaxial layer concentration strongly affect the threshold voltage and the output currents. Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant. When the output current density of the device increases, the source concentration, the thickness of the epitaxial layer, and the total width of the device need to be expanded. The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage. It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga2O3 MOSFET requires the epitaxial layer concentration, the channel height of the device, the thickness of the source region, and the oxide thickness of the device should be less than 5 × 1016 cm−3, less than 1.5 μm, between 0.1 μm − − 0.3 μm and less than 0.08 μm, respectively.

Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs

The low frequency noise performance of Gate-All-Around Nanowire (NW) or Nanosheet (NS) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is investigated, taking account of the impact of the device architecture, i.e., junctionless (JL) versus inversion-mode (IM) and process variations for the gate metal. The horizontal devices are characterized by 1/f noise, dominated by the number fluctuation mechanism, so that the power spectral density (PSD) is directly proportional with the trap density in the gate stack. The average 1/f noise PSD is becoming smaller going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices on bulk silicon and, finally, vertical NWFETs with a substrate source contact. At low currents and frequencies below 1 kHz the 1/f noise in the vertical NWs is, in contrast to the horizontal devices, controlled by mobility fluctuations. In these devices white noise is observed above 1 kHz.

Analysis of SEGR in Silicon Planar Gate Super-Junction Power MOSFETs

This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). When an incident heavy-ion strike is perpendicular to the gate oxide, the SEGR tolerances of SJ power MOSFETs (SJMOSs) and VDMOSs are similar. But, for heavy-ion strikes that are at different angles, SJMOS has better SEGR tolerance than VDMOS. This improved performance of SJMOS is due to the presence of an additional horizontal electric field component in SJMOS devices. This is validated using the experimental data and simulation results in this article.

Vertical β-Ga₂O₃ Power Transistors: A Review

With projected performance advantages over silicon and incumbent wide-bandgap compound semiconductors, gallium oxide (Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) has garnered worldwide attention as an ultrawide-bandgap semiconductor material suitable for high-voltage, high-temperature, and radiation-hard electronics. Thanks to recent breakthroughs in crystal growth and device processing technologies, the research and development of vertically oriented Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> power transistors has made rapid strides. In this article, we review the important engineering achievements and performance milestones of the two major types of vertical Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> transistors-current aperture vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) and vertical fin-channel MOSFETs. Challenges underlying the unique processing approaches to these devices and their implications on device reliability are also discussed.

(Invited) Fundamentals and Process Technologies of Current Aperture Vertical Ga2O3 MOSFETs

Ga2O3 has exploded onto the semiconductor landscape for next-generation power electronics because its enticing material properties, most notably a large critical field strength stemming from its ultra-wide bandgap of 4.5 eV, promise miniaturized circuits and systems with high conversion efficiency. High-quality native substrates produced by melt-growth methods offer an economical platform to this technology. Ga2O3 transistors reported to date have predominantly taken on a lateral geometry, yet vertical switching devices are desirable for applications that demand high voltage ratings and high power levels since they allow for large current drives, simplified thermal management, and superior field termination. Capitalizing on cost-effective ion implantation technologies for shallow donor (silicon) and deep acceptor (nitrogen) doping of Ga2O3 with efficient dopant activation at a low thermal budget, we developed both depletion-mode (D-mode) [1] and enhancement-mode (E-mode) [2] current aperture vertical Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs).The vertical Ga2O3 MOSFETs were fabricated on low-doped (~1016 cm-3) halide vapor phase epitaxial drift layers grown on single-crystal β-Ga2O3 (001) substrates [3]. In these devices, silicon ion-implanted top source contacts were electrically isolated from the bottom drain contact by a nitrogen ion-implanted current blocking layer (CBL) [4] except at an aperture bounded by CBLs through which drain current was conducted. The CBL simultaneously served as a back-barrier for a top-gated lateral channel defined by another silicon ion implantation step. D-mode devices delivered a drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 mΩ·cm2, and an output current on/off ratio of over 108. E-mode devices, whose positive threshold voltage was attained by appropriately designing the channel doping concentration such that the channel was fully depleted at 0-V gate bias, showed a high output current on/off ratio of 2×107 despite a nonideal MOS interface that limited the maximum drain current density to <0.1 kA/cm2. Both D-mode and E-mode devices did not exhibit current collapse in pulsed measurements when subjected to off-state voltage stress; however, their hard breakdown occurred prematurely owing to leakage through the CBLs, a deficiency expected to be readily overcome with an optimized nitrogen implantation process. Further details regarding fabrication, performance, and physics of the devices, as well as potential directions for future development, will be discussed in the talk. The demonstration of planar-gate vertical Ga2O3 transistors based on a highly manufacturable all-ion-implanted process greatly enhances the prospects for Ga2O3-based power electronics applications.[1] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, 431 (2019).[2] M. H. Wong, H. Murakami, Y. Kumagai, and M. Higashiwaki, Proc. 77th Device Research Conference (2019).[3] H. Murakami, K. Nomura, K. Goto, K. Sasaki, K. Kawara, Q. T. Thieu, R. Togashi, Y. Kumagai, M. Higashiwaki, A. Kuramata, S. Yamakoshi, B. Monemar, and A. Koukitu, Appl. Phys. Express 8, 015503 (2015).[4] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018).

Demonstration of 1200 V/1.4 mΩ cm2 vertical GaN planar MOSFET fabricated by an all ion implantation process

We present a vertical GaN planar metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated by an all ion implantation process. The fabricated MOSFET shows an on-resistance of 2.78 mΩ cm2 and a breakdown voltage of 1200 V, by applying the short cell pitch design to reduce the on-resistance and a Mg and N sequential implantation to improve the breakdown voltage of the pn-junction. By evaluating each on-resistance component in the fabricated vertical GaN planar MOSFET using the simultaneously formed test structures, an effective on-resistance of the active region excluding the source parasitic resistance is 1.4 mΩ cm2. Consequently, it was demonstrated that an all ion implantation process can fabricate a vertical GaN planar MOSFET with a high breakdown voltage and low on-resistance. This result will greatly contribute to the realization of GaN power devices.

Optimal design of junctionless double gate vertical MOSFET using hybrid Taguchi-GRA with ANN prediction

Random parameter variations have been an influential factor that deciding the performance of a metal-oxide-semiconductor field effect transistor (MOSFET), especially in nano-scale regime. Thus, controlling the variation of those parameters becomes extremely crucial in order to attain an acceptable performance of an ultra-small MOSFET. This paper proposes an approach to optimally design a n-type junctionless double-gate vertical MOSFET (n-JLDGVM) via hybrid Taguchi-grey relational analysis (GRA) with artificial neural networks (ANN) prediction. The device is designed using a combination of 2-D simulation tools (Silvaco) and hybrid Taguchi-GRA with a well-trained ANN prediction. The investigated device parameters consist of channel length (Lch), pillar thickness (Tp), channel doping (Nch) and source/drain doping (Nsd). The optimized design parameters of the device demonstrate a tolerable magnitude of on-state current (ION), off-state current (IOFF), on-off ratio, transconductance (gm), cut-off frequency (fT) and maximum oscillation frequency (fmax), measured at 2344.9 µA/µm, 2.53 pA/µm, 927 x 106, 4.78 mS/µm, 121.5 GHz and 2469 GHz respectively.

Extraction of the active acceptor concentration in (pseudo-) vertical GaN MOSFETs using the body-bias effect

We report and discuss the performance of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET). The trench gate structure of the MOSFET is uniformly covered with an Al2O3 dielectric and TiN electrode material, both deposited by atomic layer deposition (ALD). Normally-off device operation is demonstrated in the transfer characteristics. Special attention is given to the estimation of the active acceptor concentration in the Mg doped body layer of the device, which is crucial for the prediction of the threshold voltage in terms of device design. A method to estimate the electrically active dopant concentration by applying a body bias is presented. The method can be used for both pseudo-vertical and truly vertical devices.Since it does not depend on fixed charges near the channel region, this method is advantageous compared to the estimation of the active doping concentration from the absolute value of the threshold voltage.