(Invited) Fundamentals and Process Technologies of Current Aperture Vertical Ga2O3 MOSFETs

Abstract

Ga2O3 has exploded onto the semiconductor landscape for next-generation power electronics because its enticing material properties, most notably a large critical field strength stemming from its ultra-wide bandgap of 4.5 eV, promise miniaturized circuits and systems with high conversion efficiency. High-quality native substrates produced by melt-growth methods offer an economical platform to this technology. Ga2O3 transistors reported to date have predominantly taken on a lateral geometry, yet vertical switching devices are desirable for applications that demand high voltage ratings and high power levels since they allow for large current drives, simplified thermal management, and superior field termination. Capitalizing on cost-effective ion implantation technologies for shallow donor (silicon) and deep acceptor (nitrogen) doping of Ga2O3 with efficient dopant activation at a low thermal budget, we developed both depletion-mode (D-mode) [1] and enhancement-mode (E-mode) [2] current aperture vertical Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs).The vertical Ga2O3 MOSFETs were fabricated on low-doped (~1016 cm-3) halide vapor phase epitaxial drift layers grown on single-crystal β-Ga2O3 (001) substrates [3]. In these devices, silicon ion-implanted top source contacts were electrically isolated from the bottom drain contact by a nitrogen ion-implanted current blocking layer (CBL) [4] except at an aperture bounded by CBLs through which drain current was conducted. The CBL simultaneously served as a back-barrier for a top-gated lateral channel defined by another silicon ion implantation step. D-mode devices delivered a drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 mΩ·cm2, and an output current on/off ratio of over 108. E-mode devices, whose positive threshold voltage was attained by appropriately designing the channel doping concentration such that the channel was fully depleted at 0-V gate bias, showed a high output current on/off ratio of 2×107 despite a nonideal MOS interface that limited the maximum drain current density to <0.1 kA/cm2. Both D-mode and E-mode devices did not exhibit current collapse in pulsed measurements when subjected to off-state voltage stress; however, their hard breakdown occurred prematurely owing to leakage through the CBLs, a deficiency expected to be readily overcome with an optimized nitrogen implantation process. Further details regarding fabrication, performance, and physics of the devices, as well as potential directions for future development, will be discussed in the talk. The demonstration of planar-gate vertical Ga2O3 transistors based on a highly manufacturable all-ion-implanted process greatly enhances the prospects for Ga2O3-based power electronics applications.[1] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, 431 (2019).[2] M. H. Wong, H. Murakami, Y. Kumagai, and M. Higashiwaki, Proc. 77th Device Research Conference (2019).[3] H. Murakami, K. Nomura, K. Goto, K. Sasaki, K. Kawara, Q. T. Thieu, R. Togashi, Y. Kumagai, M. Higashiwaki, A. Kuramata, S. Yamakoshi, B. Monemar, and A. Koukitu, Appl. Phys. Express 8, 015503 (2015).[4] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018).