(Invited) Vertical Ga2O3 Transistors Fabricated By Ion Implantation Doping

Abstract

The groundbreaking demonstration of the first single-crystal gallium oxide (Ga2O3) transistors in 2011 galvanized intensive international research activities into the science and engineering of this new oxide semiconductor [1]. Much of the research and development has been motivated and inspired by the unique material properties of Ga2O3 based on an extremely large bandgap of 4.5 eV and the availability of large-size, high-quality, affordable single-crystal wafers produced from melt-grown bulk crystals. For the past several years, world-wide efforts on the development of Ga2O3 transistors have mostly been devoted to lateral field-effect transistors (FETs). However, as is well known, a vertical device geometry is much more suitable for high-voltage and/or high-current applications than a lateral geometry, because the former allows for high current drives without having to enlarge the device chip size, simplified thermal management, and far superior field termination. In this talk, we will present our state-of-the-art vertical Ga2O3 FET technologies. We fabricated depletion-mode vertical Ga2O3 metal-oxide-semiconductor FETs (MOSFETs) with a current aperture formed by buried current blocking layers (CBLs) [2]. The devices were fabricated on a 5-µm-thick n-Ga2O3 drift layer with a Si doping density of 2.5×1016 cm-3 grown by halide vapor phase epitaxy (HVPE) on an n +-Ga2O3 (001) substrate [3]. Three ion implantation process steps were employed to form Si-doped n +-regions (Si=5×1019 cm-3, 0.1-µm-thick box profile) for the source ohmic contacts, a Si-doped n-channel (Si=1.5×1018 cm-3, 0.15-µm-thick box profile), and nitrogen (N)-doped p-type CBLs in the HVPE drift layer. N was ion-implanted at an energy of 480 keV and a dose of 4×1013 cm-2, followed by thermal annealing at 1100°C for activation. Note that we found that N atoms doped in Ga2O3 act as deep acceptors to compensate background electrons, and that our development of the N-ion implantation doping process was a technological breakthrough [4], which would lead to the fabrication of planar-gate vertical MOSFETs. The current aperture vertical MOSFET showed decent device characteristics such as a maximum drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 mΩ·cm2, and a high drain current on/off ratio of over eight orders of magnitude. The off-state breakdown voltage was limited to less than 30 V owing to the large electric field in the Al2O3 gate dielectric, but can be increased by improving material quality of the gate dielectric and optimizing doping schemes. This work was partially supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: New Energy and Industrial Technology Development Organization). [1] M. Higashiwaki, K. Sasaki, A. Kuramata, T. Masui, and S. Yamakoshi, Appl. Phys. Lett. 100, 103504 (2012). [2] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, in press (2019). [3] K. Goto, K. Konishi, H. Murakami, Y. Kumagai, B. Monemar, M. Higashiwaki, A. Kuramata, and S. Yamakoshi, Thin Solid Films 666, 182 (2018). [4] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018).