Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance.

Johannes Svensson,Adam Jönsson,Lars-Erik Wernersson,Erik Lind,Elisabetta Maria Fiordaliso,Markus Hellenbrand

doi:10.1021/acsaelm.1c00729

Abstract

Thin vertical nanowires based on III–V compound semiconductors are viable candidates as channel material in metal oxide semiconductor field effect transistors (MOSFETs) due to attractive carrier transport properties. However, for improved performance in terms of current density as well as contact resistance, adequate characterization techniques for resolving doping distribution within thin vertical nanowires are required. We present a novel method of axially probing the doping profile by systematically changing the gate position, at a constant gate length Lg of 50 nm and a channel diameter of 12 nm, along a vertical nanowire MOSFET and utilizing the variations in threshold voltage VT shift (∼100 mV). The method is further validated using the well-established technique of electron holography to verify the presence of the doping profile. Combined, device and material characterizations allow us to in-depth study the origin of the threshold voltage variability typically present for metal organic chemical vapor deposition (MOCVD)-grown III–V nanowire devices.

Highlights

Vertical III−V nanowires (NWs) provide new capabilities in many semiconductor device technologies such as light-emitting diodes,[1] solar cells,[2,3] and improved complementary metaloxide semiconductor (CMOS) transistor architectures attractive beyond the scaling limit for the conventional Si technology.[4−8] Thin nanowires allow for greater flexibility in material integration due to their smaller footprint, which enables a larger lattice mismatch by radial strain relaxation
We present a novel characterization method used to probe the axial doping distribution in high-performance and scaled metal−oxide−semiconductor field-effect transistors (MOSFETs) by varying the gate position along a vertical InAs nanowire and evaluating the resulting threshold voltage (VT) shift
Device schematics and representative transfer characteristics for metal oxide semiconductor field effect transistors (MOSFETs) with varying gate position along the vertical nanowire are presented in Figure 2

Summary

■ INTRODUCTION

Vertical III−V nanowires (NWs) provide new capabilities in many semiconductor device technologies such as light-emitting diodes,[1] solar cells,[2,3] and improved complementary metaloxide semiconductor (CMOS) transistor architectures attractive beyond the scaling limit for the conventional Si technology.[4−8] Thin nanowires allow for greater flexibility in material integration due to their smaller footprint, which enables a larger lattice mismatch by radial strain relaxation. The expected doping profile can be predicted based on geometry and growth conditions, where the gradient from the Sn-doped bottom segment is estimated to be in the order of the gold particle size, in our case about 30 nm (see the Methods section for detailed growth parameters).[15] The nanowires are radially overgrown with a 5 nm n-doped InAs shell (Figure 1b), which contributes to improved contact resistance for the final devices.[30] Vertical GAA MOSFET devices are formed by following a self-aligned gate last process The use of multiple nanowires in each device provides beneficial averaging with respect to process conditions within the array, which serves to suppress unwanted variations of electrical properties for similar devices.[32]

■ RESULTS

■ METHODS

■ REFERENCES