Abstract
Structure for a vertical MOSFET (metal oxide semiconductor field effect transistor) is one of the solutions for fabricating the under 50nm channel length transistor. Compared with conventional devices, new features include vertical channel structure, dielectric pocket, FILOX (fillet local oxidation) oxide layer and PolySiGe region. This vertical MOSFET work is put into the ITRS (International Technology Roadmap of Semiconductor) roadmap. We wish to realize the 22nm surround gate MOSFETs technology in 2009.
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