Vertical JFET Research Articles

Design of Monolithically Integrated Temperature Sensors in 4H-SiC JFETs

In this paper we study and compare two designs of a temperature sensor monolithically integrated to a vertical SiC JFET. One sensor utilizes the standard JFET P+ aluminum gate implantation scheme. The advantage of this sensor is that the integration with a JFET process flow can be achieved with no additional process steps or mask layers. The other sensor uses a combination P-body and a low energy P+ implantation scheme, typically seen in MOSFETs. Both sensors exploit the variation of resistance with temperature of Al doped SiC. Drift-Diffusion simulations of both designs are carried out at fixed temperatures, exhibiting an excellent ~53% relative reduction in sensor resistance from 300 to 450K. However, neither design shows linear behavior with temperature, beginning to saturate at 450K. Electrothermal simulations are also deployed to verify the sensor robustness as the sensor is locate relatively far from the JFET junction. Due to the high thermal conductivity of SiC, the sensor average temperature follows closely the junction temperature. Current crowding (or 2D effects) close to the contact edges is observed in both sensors. We also deploy a simple analytical model to calculate the resistance as a function of the temperature for both sensors. The model agrees with the drift-diffusion calculations, however due to the 2D nature of current flow, a maximum 19.6% relative error is obtained. In general, both sensors deployed similar relative sensitivity, however the P-body sensor resistance changes in a range of 10.6kΩ to 4.95kΩ compared to 700Ω to 330Ω for the P+ sensor.

Design and performance analysis of GaN vertical JFETs with ion-implanted gates

We present a comprehensive performance analysis of vertical GaN JFETs via TCAD simulation with unique considerations for gates formed by Mg ion implantation into GaN. The dependence of the specific ON-resistance and pinch-off voltage on the gate and channel design parameters is first evaluated for a JFET with abrupt gate-channel junctions. Then, the influence of the gate acceptor concentration and distribution is studied to elucidate the consequences of incomplete acceptor activation or acceptor diffusion resulting from specialized post-implantation annealing techniques necessary for the activation of p-GaN. Examples of normally-ON and normally-OFF designs with 1.7 kV breakdown voltage for 1.2 kV applications are chosen for the activation and diffusion studies to demonstrate how the pinch-off and conduction characteristics are affected for different channel widths and doping concentrations conducive to each type of operation. Record low specific ON-resistance below 1 mΩ cm2 is predicted for both, but gate acceptor diffusion increases the channel resistance, especially for JFETs designed to be normally-OFF.

Breakthrough Short Circuit Robustness Demonstrated in Vertical GaN Fin JFET

Insufficient short-circuit (SC) robustness of currently commercial GaN power devices, i.e., the high electron mobility transistors (HEMTs), is a key roadblock for their applications in automotive powertrains. At a 400 V bus voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BUS</sub> ), the SC withstanding time ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</sub> ) of commercial GaN HEMTs is typically below 1 μs, far below the usual system requirement (>10 μs). This letter presents breakthrough short-circuit capability in a vertical GaN fin-channel junction-gate field-effect transistor (Fin-JFET). The Fin-JFET is normally <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> with a 0.7 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> specific <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -resistance and 800 V avalanche breakdown voltage (BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AVA</sub> ) at the room temperature. The gate driver in the short-circuit test was designed to be identical to that in device switching applications. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SC</sub> of GaN Fin-JFETs was measured to be 30.5 μs at a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BUS</sub> of 400 V, 17.0 μs at 600 V, and 11.6 μs at 800 V, all among the longest reported for 600–700 V normally <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> transistors. In addition, GaN Fin-JFETs failed open in these tests and retained BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AVA</sub> after failure, which is highly desirable for system applications. In the repetitive 10 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> s, 400 V short-circuit tests, GaN Fin-JFETs showed no degradation after 30 000 cycles. Furthermore, to the best of our knowledge, this is the first report of a power transistor with good short-circuit ruggedness at a bus voltage close to its BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AVA</sub> . The underlying mechanism is the unique avalanche-through-fin in the Fin-JFET, which is validated by mixed-mode TCAD simulations and unclamped inductive switching tests. These results reveal the inherent ruggedness of GaN Fin-JFETs in the concurrent presence of short-circuit and overvoltage in power electronics systems.

Performance of wide-bandgap discrete and module cascodes at sub-1 kV: GaN vs. SiC

Wide-bandgap (WBG) based cascode devices combine the advantages of the gate driveability and reliability of silicon MOSFETs with the power conversion efficiency and switching rate of wide bandgap devices. A low voltage (rated at ~20–30 V) silicon MOSFET drives a vertical JFET for the SiC cascode whereas for the GaN cascode, it drives a lateral GaN HEMT. This paper presents the first systematic comparison of the WBG discrete and module cascodes considering conduction losses, 3rd quadrant operation, switching performance, unclamped switching performance, spontaneous switchings, crosstalk as well as the temperature sensitivities. The results show that the GaN cascode outperforms the SiC cascode considerably in switching performance, however, demonstrates higher conduction losses with more temperature sensitivity in GaN. In this paper, it is also shown experimentally and theoretically that the switching rate in the GaN cascode is more sensitive to the gate resistance compared to the SiC cascode. While turn-ON dIDS/dt and dVDS/dt have positive temperature coefficients in the SiC cascode and negative coefficients in the GaN cascode, the SiC cascode is shown to be more UIS rugged, whereas the GaN cascode is incapable of unclamped inductive switching. The impact of unwanted switching on both GaN and SiC cascodes are also shown, indicating that there is a range of optimum gate resistances where un-wanted turn-on and turn-off switchings can be avoided, with the GaN cascode experiencing a higher crosstalk-induced gate voltage due to its higher switching rates.

Evaluation of radiation hardness of High-Voltage silicon vertical JFETs

In the future ATLAS Inner Tracker, each silicon strip module will be equipped with a switch able to separate the high voltage supply from the sensor in case the latter becomes faulty. The switch, placed in between the HV supply and the sensor, needs to sustain a high voltage in its OFF state, to offer a low resistance path for the sensor leakage current in the ON state, and be radiation hard up to 1.2⋅ 1015 neq/cm2 along with other requirements. While GaN JFETs have been selected as suitable rad-hard switch, a silicon vertical HV-JFET was developed by Brookhaven National Laboratory as an alternative option. Pre-irradiation results showed the functionality of the device and proved that the silicon HV-JFET satisfied the pre-irradiation requirements for the switch. To assess its suitability after irradiation, a few p-type HV-JFETs have been neutron irradiated at Jozef Stefan Institute (JSI, Ljubljana, Slovenia). This paper reports the static characterization of these irradiated devices and the TCAD numerical simulations used to get an insight of the physics governing the post-irradiation behaviour.

Analytical model for the double-gate JFET applied to SiC power JFETs

ABSTRACT An analytical and physical model for the double-gate vertical JFET (VJFET) with a lateral and a vertical channels is presented. The model has been implemented and tested in the SABER circuit simulator and its modeling language, MAST. The model includes an asymmetric representation of the lateral channel which is the main contribution of the paper. The blocking condition depends on both gate voltages. It is a key issue of the VJFET model and it is presented in details. Each junction of the structure is represented as a Shockley pn-junction model in parallel with the associated junction capacitance. The comparison between simulations and experiments yields to satisfying results, both in static and dynamic conditions. The analysis of the remaining difficulties to be solved is given.

Fabrication and electrical characterization of High-Voltage silicon JFETs

Motivated by the need of a rad-hard switch to be used in the future ATLAS Inner Tracker detector (ITk), at Brookhaven National Laboratory we conceived a High-Voltage silicon vertical JFET capable of satisfying most of the strict specifications required for such a switch. By using the available planar technology for the silicon processing, we fabricated in our Clean Room dedicated batches of HV JFETs, first n-type and then p-type channel JFETs. The electrical characterization showed in particular high voltage handling capabilities in the OFF state, for both types of JFETs. In this paper, we describe the design, the fabrication steps and we report the electrical characterization.

A HV silicon vertical JFET: TCAD simulations

In the future ATLAS Inner Tracker detector (ITk), several silicon strip modules will be biased by a single High-Voltage (HV) line, so that a switch between each strip sensor and the HV line is required to disconnect faulty sensors. Such a switch must satisfy strict requirements, such as being radiation hard, being able to sustain high voltages in the OFF state and being able to operate in a high magnetic field. At Brookhaven National Laboratory we conceived a new kind of solid-state switch that can potentially meet all the specs: it is a HV silicon vertical JFET. Before designing and fabricating the JFET, we did a study using numerical TCAD simulations that demonstrate the feasibility of fabricating the device in a standard planar technology. We report such simulations, highlighting in particular a few key parameters to which the JFET performances are most sensitive.

First fabrication of a silicon vertical JFET for power distribution in high energy physics applications

A new vertical JFET transistor has been recently developed at the IMB-CNM, taking advantage of a deep-trenched 3D technology to achieve vertical conduction and low switch-off voltage. The silicon V-JFET transistors were mainly conceived to work as rad-hard protection switches for the renewed HV powering scheme (HV-MUX) of the ATLAS upgraded tracker. This work presents the features of the first batch of V-JFETs produced at the IMB-CNM clean room, together with the results of a full pre-irradiation characterization of the fabricated prototypes. Details of the technological process are provided and the outcome quality is also evaluated with the aid of reverse engineering techniques. Concerning the electrical performance of the prototypes, promising results were obtained, already meeting most of the HV-MUX specifications, both at room and below-zerotemperatures.

Capacitances in 4H-SiC TSI-VJFETs

Internal device capacitances in 4H-SiC based devices play an important role in determining their performances. In the present work, an analysis of the capacitance measurements in 4H-SiC trenched and single-implanted (TSI) gate vertical JFET TSI-VJFETs has been undertaken. Physical parameters such as threshold voltage and the related to its value effective channel length as well as channel layer and drift layer doping profiles have been extracted. The measured internal capacitances have been modeled by various models based on device physics.

Gamma irradiation damage on the vertical JFET transistors fabricated at the IMB-CNM

A new vertical JFET technology, based on a 3D trenched design, has been developed at the IMB-CNM. These transistors are conceived to work as rad-hard protection switches in the renewed High Voltage powering scheme for the Upgrade ATLAS ITk strip detectors. The first fabricated wafers have been fully characterized and the V-JFET performance is very close to the required specifications, showing excellent agreement with simulations. In this work the performance of the fabricated prototypes is tested under harsh ionizing radiation conditions. The variation of the main figures of merit is evaluated as a function of the Total Ionising Dose (TID) and the impact of different design parameters and fabrication strategies are compared. A final study, performed with the aid of TCAD simulations, is also included to understand the effects of the ionization damage observed on the V-JFET performance.

Design and Application of High-Voltage SiC JFET and Its Power Modules

This paper presents the structural design, prototype development, and testing of high-voltage silicon carbide (SiC) trenched-and-implanted vertical JFETs. Key design factors including drift layer doping concentration and thickness, channel dimensions, and termination structures are studied with numerical simulations. Devices are then fabricated in our research level facilities. The fabricated device has an active region of 4 mm2 and can conduct a current of 2.8 A at a drain voltage of 3 V and a gate bias of 2.9 V. With a negative gate bias of −5 V, the breakdown voltage is over 4500 V. Based on these devices, two modules are designed and developed. One is a 4500 V/50-A SiC JFET power module. The other one is an all-SiC power module with SiC JFETs and SiC JBS diodes. And the second one is also evaluated in a high-frequency boost converter. The testing results show that this All-SiC module is capable of working at a frequency up to 100 kHz with both turn-on and turn-off time less than 150 ns. A high converter efficiency of 97% is obtained at a 50-kHz switching frequency and the efficiency is 95% at a switching frequency of 100 kHz. This paper demonstrates that the SiC JFET and its power module can be used for SiC device applications in medium-voltage range.

Modelling of 4H-SiC VJFETs with Self-Aligned Contacts

Purely vertical 4H-SiC JFETs have been modeled by using three different approaches: the analytical model, the finite element model and the compact model. The results of the modeling have been compared with experimental results on a series of fabricated self-aligned devices with two different channel lengths (0.3 and 1.1μm) and various channel widths (1.5, 2, 2.5, 3, 4 and 5 μm). For all the considered models I-V and C-V characteristics could be satisfactorily simulated.

Rad-hard vertical JFET switch for the HV-MUX system of the ATLAS upgrade Inner Tracker

This work presents a new silicon vertical JFET (V-JFET) device, based on the trenched 3D-detector technology developed at IMB-CNM, to be used as a switch for the High-Voltage powering scheme of the ATLAS upgrade Inner Tracker. The optimization of the device characteristics is performed by 2D and 3D TCAD simulations. Special attention has been paid to the on-resistance and the switch-off and breakdown voltages to meet the specific requirements of the system. In addition, a set of parameter values has been extracted from the simulated curves to implement a SPICE model of the proposed V-JFET transistor. As these devices are expected to operate under very high radiation conditions during the whole experiment life-time, a study of the radiation damage effects and the expected degradation of the device performance is also presented at the end of the paper.

The Influence of Neutron Irradiation on Electrical Characteristics of 4H-SiC Power Devices

Commercial 1200V and 1700V MPS diodes and 1700V vertical JFETs produced on 4H-SiC n-type epilayers were neutron irradiated with fluences up to 4x1014 cm-2 (1 MeV neutron equivalent Si). Radiation defects and their effect on carrier removal were investigated by capacitance deep-level transient spectroscopy, I-V and C-V measurement. Results show that neutron irradiation introduces different point defects giving rise to deep acceptor levels which compensate nitrogen doping of the epilayer. The carrier removal rate increases linearly with nitrogen doping. Introduced defects deteriorate ON-state characteristics of irradiated devices while their effect on blocking characteristics is negligible. The effect of neutron irradiation can be simulated by TCAD tools using a simple model accounting for introduction of one dominant deep level (Z1/Z2 centre).

IR Lock-In Thermography Analysis to Evidence Dynamic Mis-Behavior of SiC Device Prototypes

This paper deals with the geometry of a high voltage (1200 V) vertical JFET made with 4H silicon carbide, inspired by SIT or commercial solutions like Semisouth's one (principle exposed in Fig. 1). A first layout was designed allowing an easy integration of a free-wheeling diode. Indeed with the maturity of SiC JFET fabrication process, nowadays' trend is the high integration level of a complete power electronics system. This paper will focus on the distribution of the gate potential or the source current across the device and the relation that could be done with the switching delay. The measurements start with the classical I–V static characterization from room temperature till 225°C. After packaging the best dies, the switching behavior is studied. Gate bias and temperature dependence is also investigated. In order to fully understand the conducting/blocking or switching mechanisms, some further measurements using lock-in infrared thermography (LIRT) technique was led. Thus, with this complete characterization methodology the device layout can be improved.

Study of Temperature Dependent Punch-through Behavior in 4H-SiC VJFET: TCAD Simulation

In this work, the effect of gate doping and temperature is analyzed on breakdown voltages in 4H-SiC based vertical JFET. The physical model has a good agreement with wide range of temperatures showing that breakdown voltage indeed varies with temperature and the device exhibits negative temperature coefficient. Maximum breakdown voltage of 2133V is observed with doping concentration of 5×1018 cm-3 at room temperature, which is approximately same (2118V) when doping was 3 x 1018 cm-3 but 34% higher when doping was 1 x 1018 cm-3. Using finite element simulation, the distribution of electric field and impact ionization as a function of temperature and gate doping concentration is also analyzed. During the depth dependence electric field study results, it is clarified that punch through behavior at the interface of drift (n−) and drain (n+) region is prominent.

Analog and Logic High Temperature Integrated Circuits based on SiC JFETs

Harsh environment applications such as electrical actuation on military and commercial aircraft, advanced engine controls, downhole energy exploration, propulsion systems of hybrid and all electric vehicles, and space exploration require sensor interfaces, control circuits, and power systems with electronics capable of operating at high temperatures. Wide band-gap materials such as SiC can be used to build devices with high operating temperatures due to their fundamental material properties. This paper presents initial results on developing basic analog and logic integrated circuits based on SiC JFET technology. Analog and logic integrated circuits were built using enhancement vertical channel lateral JFET transistors, metal film resistors and lateral p-n diodes. The analog circuits built include different types of operational amplifiers. The logic circuits include NOT, NAND, AND, NOR and OR gates. Transistors and integrated circuits were packaged in ceramic DIP packages and tested at temperatures up to 500 °C. The tested JFETs show proper operation up to the maximum tested temperature of 500 °C. The operational amplifiers remained functional at temperatures up to 430 °C. Basic logic circuits showed proper operation up to the maximum tested temperature of 500 °C.

1000V Vertical JFET Using Bulk GaN

Bulk GaN substrates with low defect density are now commercially available. This material enables the fabrication of vertical GaN devices with high breakdown voltage, and excellent electrical performance and power device figure of merit. In this paper, we present a 1000V Vertical JFET that has a positive threshold of 1V. The normally-off FET integrates a hetero-junction in the design to improve the transconductance and enable efficient switching operation into the 10s of MHz.

Modeling of the Steady State and Switching Characteristics of a Normally Off 4H-SiC Trench Bipolar-Mode FET

The electrical characteristics of a normally off 4H-silicon carbide (SiC) bipolar-mode FET are investigated by means of a careful design activity and an intensive simulation study useful for a first-time-ever realization of this device in SiC. Specific physical models and parameters strictly related to the presently available 4H-SiC technology are taken into account. The device basically consists of a trench vertical JFET operating in the bipolar mode that takes full advantage of the superior material properties. A drain-current density up to 500 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a forced current gain on the order of 50, and a specific on-resistance as low as 1.3 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> are calculated for a 1.3-kV blocking voltage device. The turn-off delay is on the order of a few nanoseconds. The presented analysis is supported by experimental results on the p-i-n diodes embedded in the device structure.