Vertical GaN Devices Research Articles

A Novel Isolation Approach for GaN-Based Power Integrated Devices.

This paper introduces a novel technology for the monolithic integration of GaN-based vertical and lateral devices. This approach is groundbreaking as it facilitates the drive of high-power GaN vertical switching devices through lateral GaN HEMTs with minimal losses and enhanced stability. A significant challenge in this technology is ensuring electrical isolation between the two types of devices. We propose a new isolation method designed to prevent any degradation of the lateral transistor's performance. Specifically, high voltage applied to the drain of the vertical GaN power FinFET can adversely affect the lateral GaN HEMT's performance, leading to a shift in the threshold voltage and potentially compromising device stability and driver performance. To address this issue, we introduce a highly doped n+ GaN layer positioned between the epitaxial layers of the two devices. This approach is validated using the TCAD-Sentaurus simulator, demonstrating that the n+ GaN layer effectively blocks the vertical electric field and prevents any depletion or enhancement of the 2D electron gas (2DEG) in the lateral GaN HEMT. To our knowledge, this represents the first publication of such an innovative isolation strategy between vertical and lateral GaN devices.

Fabrication of Ultralow‐Bevel Angle Mesa Structures for Vertical GaN Devices

Low‐angle bevel mesa structures are the key technological ideas needed to produce high‐quality vertical GaN devices. Nevertheless, the literature lacks sufficient information regarding the techniques that can yield the best results for obtaining the bevel angles smaller than approximately 5°.[1] Notably, for high p–n junctions NA/ND ratios, such low angles are necessary for the application of negative beveled edge termination and the efficient lowering of electric field at the surface.[1–6] In this work, the optimization of the beveled‐mesa fabrication technique for vertical GaN devices is demonstrated employing a plasma etching of the photoresist mask fabricated using a reflow process. By adjusting the resist reflow process parameters, in particular various BCl3 Cl2−1 ratios and inductively coupled plasma–reactive ion etching plasma power, a range of beveled mask angles as low as 10°–12° is achieved. However, those processes all show etching selectivity close to 1:1 between GaN and the photoresist. Even lower bevel mesa angles are reported for a novel process optimization that resulted in improving GaN to photoresist selectivity by a factor of 5–10. As a result, even smaller bevel mesa angles close to 1°–2° are able to be attained. The developed approach has the advantage of being relatively simple and cost effective.

Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD

Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications. Being still in an early development phase, vertical GaN devices are yet to be fully optimized and require careful studies to foster their development. In this work, we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs (TMOS’s) provided by TCAD simulations, enhancing the dependability of the adopted process optimization approaches. Specifically, two different TMOS devices are compared in terms of transfer-curve hysteresis (H) and subthreshold slope (SS), showing a ≈ 75% H reduction along with a ≈ 30% SS decrease. Simulations allow attributing the achieved improvements to a decrease in the border and interface traps, respectively. A sensitivity analysis is also carried out, allowing to quantify the additional trap density reduction required to minimize both figures of merit.

Route Toward Commercially Manufacturable Vertical GaN Devices

Route Toward Commercially Manufacturable Vertical GaN Devices

Optimization of Step-Etched Junction Termination Extensions for Vertical GaN Devices

Optimization of Step-Etched Junction Termination Extensions for Vertical GaN Devices

Research on vertical GaN devices based on gradient Al components

A groove-gate power device with a linearly gradient Al composition P-type AlGaN superjunction (abbreviated as LG-SJCAVET) is proposed, which uses polarized P-type AlGaN material instead of the traditional P-type GaN buried layer, avoiding the technical bottleneck of achieving high-aspect-ratio P-type doping in GaN materials. Simulation results show that, under the same structural parameters, the breakdown voltage of LG-SJCAVET reaches 2954V, and the on-resistance is 1.669 mΩ⋅cm2, which is due to no current flowing through the P-pillar, resulting in an increase in on-resistance, while affecting the DC characteristics of the device. The power figure of merit of the device is 5.27 GW/cm2, which is 67.11% and 27.38% higher than that of the traditional device and P-type GaN buried layer device, respectively. Therefore, the LG-SJCAVET device solves the problems of the high technical difficulty of the traditional P-type GaN buried layer process, difficulty in activating acceptor impurities, and poor thermal stability of the device, exhibiting superior breakdown voltage characteristics.

Fabrication of Quasi-Vertical GaN-On-SiC Trench MOSFETs

We demonstrate quasi-vertical GaN MOSFETs fabricated on SiC substrates. The GaN epitaxial layers were grown via MOCVD on 100 mm 4H-SiC wafers, with the device structure consisting of a 2.5 μm drift layer and a Mg doped p-GaN body. The fabricated transistors exhibit normally-off characteristics, with low off-state leakage behavior and an on/off ratio of over . The specific on-resistance was measured to be which compares favorably to devices fabricated on other foreign substrates. Our results demonstrate an alternative substrate for realizing vertical GaN devices, which potentially offers better material quality and thermal properties compared with other foreign substrate choices.

High Current Density Trench CAVET on Bulk GaN Substrates with Low-Temperature GaN Suppressing Mg Diffusion

We report that, for the first time, a low-temperature GaN (LT-GaN) layer prepared by metal–organic chemical vapor deposition (MOCVD) regrowth was used as a Mg stopping layer (MSL) for a GaN trench current–aperture vertical electron transistor (CAVET) with p-GaN as a carrier blocking layer (CBL). Inserting LT-GaN on top of the p-GaN effectively suppresses Mg out-diffusion into the regrown AlGaN/GaN channel, contributing to the high current capability of GaN vertical devices with a p-GaN CBL. With different MOCVD growth conditions, MSLs inserted in trench CAVETs were comprehensively investigated for the influence of MSL regrowth temperature and thickness on device performance. With the best on-state current performance obtained in this study, the trench CAVET with a 100 nm thick MSL regrown at 750 °C shows a high drain current of 3.2 kA/cm2 and a low on-state resistance of 1.2 mΩ∙cm2. The secondary ion mass spectrometry (SIMS) depth profiles show that the trench CAVET with the 100 nm thick MSL regrown at 750 °C has a dramatically decreased Mg diffusion decay rate (~39 nm/decade) in AlGaN/GaN channel, compared to that of the CAVET without a MSL (~104 nm/decade). In developing GaN vertical devices embedded with a Mg-doped p-type layer, the LT-GaN as the MSL demonstrates a promising approach to effectively isolate Mg from the subsequently grown layers.

Vertical GaN-on-GaN pn power diodes with Baliga figure of merit of 27 GW/cm2

High power vertical GaN devices are in great demand recently due to their potential on extremely high-power conversion efficiency. Here, we show vertical GaN p–n power diodes fabricated on bulk GaN substrates with an optimized guard ring structure for electrical field management and high breakdown voltage. By using a low doped (∼1015 cm−3) 28 μm thick drift layer in combination with optimized ohmic contacts, a breakdown voltage (VB) of 4.9 kV and a low specific on-resistance (RON) of 0.9 mΩ cm2 were achieved. In combination with the high breakdown voltage and low specific on-resistance, the device demonstrated a Baliga figure of merit (V2B/RON) of 27 GW/cm2.

Design of the GaN based CAVET with SiO2–InGaN hybrid current blocking layer

The emergence of vertical GaN devices solves the problem of insufficient voltage withstand capacity of horizontal GaN devices. However, the current output capability of vertical GaN devices is not comparable to that of lateral GaN devices. So we propose a Al0.3Ga0.7N/GaN current-aperture vertical electron transistor with a SiO2–In0.05Ga0.95N hybrid current-blocking layer (CBL). Through simulation and in-depth study of the proposed device, the results show that the GaN/InGaN secondary channel enhances the saturation output current of the device, achieving a saturated output current (I DSS) of 985 mA mm−1 and a transconductance (G m) of 256 mS mm−1, which are 30% and 25% higher than that of the single-channel SiO2 CBL device, respectively. The breakdown voltage is 230 V and the on-resistance (R on) is only 0.58 mΩ cm2.

(Invited) Vertical GaN Diodes: Effect of Growth Parameters, Indium Surfactants, and Device Development for High-Power Electronics

GaN has achieved widespread interest in high-power and high-speed electronics due to its wide-bandgap (WBG), large breakdown field, and high mobility compared to Si and SiC. There is also continued interest in the growth and development of GaN vertical devices owing to their advantageous properties of high current capability from backside ohmic, better field management, scaling feasibility, and enhanced thermal transport, which is not feasible with the lateral device topology. To realize the predicted high breakdown voltage and low on-resistance from vertical devices, high-quality drift layers with low unintentional doping and low compensating defects are fundamentally required. Hence, our research aims to pursue a comprehensive investigation of growth and device development with vertical GaN structures, building from the optimization of thick GaN homoepitaxy with high growth rate but low impurities, improving surface morphology using Indium as a surfactant as well as realizing punch-through field-plate p-n diodes to maximize the average electric field in high-voltage operation.Toward the goal of high-quality GaN epitaxy growth, we performed systematic studies of growth rate effects on the drift layer doping using ammonia molecular beam epitaxy (NH3 MBE) and plasma-assisted molecular beam epitaxy (PA MBE) [1]. The NH3 MBE homoepitaxy GaN demonstrated an unintentional doping (UID) of ~1015 cm-3, significantly lower than that of the conventional metalorganic chemical vapor deposition (MOCVD) reports, which can be potentially contributed by clean growth environment of MBE.We further focused on improving surface morphology using Indium as a surfactant. Through a combination of varying V/III ratios, In flux and growth temperatures, an optimal condition for surface morphology, characterized by atomic force microscopy, was achieved for fast growth rates (on the order of 1 µm/hr and beam equivalent pressures on the order of 5 × 10-7 Torr). However, excessive indium causes the surface morphology to degrade, potentially due to the enhancement of the Ga desorption from the surface as a result of the reaction of indium with ammonia for high indium fluxes. The indium surfactant can also reduce silicon impurities as revealed from the Secondary ion mass spectrometry (SIMS) (Fig. 2).Subsequently, we developed vertical p-n GaN power devices using the NH3 MBE-grown high-quality epitaxy [2]. The vertical p-n GaN diode consisted (from bottom up): ~0.25 µm of n+ GaN ([Si]: 1×1019 cm-3) buffer, ~4 µm UID GaN drift layer for n-type region, ~0.4 µm p+GaN ([Mg]: 3×1019 cm-3) for p-type region, and ~10 nm p++ GaN cap ([Mg]: 3×1020 cm-3) to support the anode ohmic contact. Circular p-n diodes of 80-100 µm diameter were fabricated with Pd/Pt anode and a backside Ti/ Au ohmic contact. The field management was achieved by field-plate of 15 µm formed with Ti/Au metals on top of a field-plate dielectric of a Al2O3 (26 nm)/ Si3N4 (205 nm) stack (Fig. 3).The p-n GaN diodes exhibited an outstanding forward J-V behavior with a low specific on-resistance (Ron,sp) of 0.28 mΩ-cm2 and a minimum ideality factor of 1.36 (Fig. 4), which are among the best achieved in vertical homoepitaxy GaN p-n diodes [2-4]. The best diodes also exhibited a breakdown voltage of > 1 kV (equipment limit 1 kV). These reverse-voltage properties imply a punch-through characteristics with peak electric field (EC) >2.6 MV/cm, as revealed by Silvaco simulation (Fig. 5). The combination of >1 kV breakdown voltage and on-resistance of 0.28 mΩ-cm2 represents one of the best performances of the p-n GaN diodes, achieved with a significantly downscaled (~4 um) drift layer compared to the MOCVD GaN p-n diodes of ≥ 8 um (Fig. 6). Work is ongoing to develop NHE MBE p-n diodes with indium surfactant-assisted drift layer growth which will be promising to further improve the surface morphology, reduce leakage, and enhance breakdown performance of the vertical devices.

A Simple Edge Termination Design for Vertical GaN P-N Diodes

Vertical power devices require significant attention to their edge termination designs to obtain higher breakdown voltages without substantial increase in ON-state resistance. A simple edge termination structure for a GaN p-n diode is proposed, comprising a full layer lightly doped p-type GaN region underneath the higher doped <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p} +\!+$ </tex-math></inline-formula> contact layer. A TCAD model of the device is developed, and removal of the portions of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> ++ cap outside of the device active area in simulations is shown to increase the device blocking voltage capability. It causes the depletion width to increase in the lightly doped p-type layer and allows it to act similar to a junction termination extension (JTE). These predictions are validated empirically, resulting in a 52% measured increase in breakdown capability after selective removal of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> ++ cap. This simple edge termination technique can be formed with only a single low-energy nitrogen implant or etching procedure, greatly increasing its manufacturability over more complex structures. Design optimization studies are pursued in TCAD to determine optimal parameter values for further improving breakdown performance. It is shown that the proposed edge termination technique can be employed to produce future high voltage vertical GaN devices without a significant gain in ON-state resistance and with wide tolerance to process variations.

A novel normally-off GaN vertical Schottky source tunnel-junction field-effect transistor

In this work, a novel normally-off GaN vertical tunnel-junction field-effect transistor (VTJFET) was proposed and investigated by the Silvaco ATLAS simulator. The topology structure and operation mechanism of the VTJFET are completely different from those of previous GaN vertical power devices. The VTJFET exhibited normally-off operation with a threshold voltage VTH of +2.5 V. The specific on-resistance Ron,sp and the breakdown voltage BV were 1.78 mΩ cm2 and 2940 V, respectively. A high on-off current ratio of 1011 and high power figure of merit (FOM) of 4.9 GW/cm2 were achieved. The Ron,sp and BV of the VTJFET are affected by the doping concentration Ndrift and thickness Tdrift of the drift layer, and a record high optimized FOM of 7.4 GW/cm2 was obtained by varying Ndrift and Tdrift. The VTJFET is intrinsically normally-off and exhibited excellent performance, providing a new direction for the development of GaN vertical devices.

(Invited) Breakthrough Avalanche and Short Circuit Robustness in Vertical GaN Power Devices

After decades of relentless efforts, GaN power devices, specifically, the lateral GaN high-electron mobility transistor (HEMT), have been commercialized in the 15-650 V classes. Owing to GaN’s competitive physical properties over Si and SiC for power electronics, GaN HEMTs allow for higher switching frequency and therefore, have already seen wide adoptions in fast chargers, wireless charging, data centers, and electrified transportation. Despite the success of lateral GaN HEMTs, a vertical device structure is usually believed to be more favorable for high-voltage, high-power devices. In the last few years, with the advent and maturity of large-diameter, low-dislocation GaN wafers on freestanding GaN substrates, a new generation of vertical GaN power devices have been developed to extend GaN’s application space beyond 650 V. Very recently, several industrial vertical GaN devices in the voltage classes of 1.2-1.7 kV have been demonstrated, which are close to commercialization.This presentation will review the key advancements in vertical GaN power devices in the past decade, with a focus on the device technologies that are being commercialized, and provide a prospective for research and development in the next decade. The devices to be covered will include two-terminal power rectifiers including the p-n diodes, Schottky barrier diodes, junction barrier Schottky diodes, and trench MIS/MOS barrier Schottky diodes. The transistors will include the trench and planar MOSFETs, current-aperture vertical electron transistors, fin-channel MOSFETs, and fin-channel JFETs. Particular emphasis will be on large-area rectifiers and transistors with a device performance superior to similarly-rated Si and SiC transistors. The newly demonstrated avalanche and short-circuit robustness in vertical GaN devices, which are lacking in lateral GaN HEMTs, as well as their underlying device physics, will also be introduced. The presentation will be concluded by a discussion of current challenges and future application spaces of vertical GaN devices, as well as emerging vertical GaN devices (e.g., superjunction) under development.

Impact of Substrate Defects on Vertical GaN Device Leakage Behavior

In this work, the effects of the substrate defects on the reverse leakage behavior of vertical GaN Schottky and p-i-n diodes are investigated. A direct connection between the reverse leakage behavior of GaN based vertical devices and the defect characteristics of the substrate was achieved. The difference in the leakage current can be as high as 6 orders of magnitude for vertical GaN p-i-n diodes at -200V, using HVPE substrate with inhomogeneous defect distributions (with dot-cores). For comparison, using HVPE substrate with uniform defect distribution (no cores), the p-i-n diodes show much more uniform leakage behavior at -200V, varying within only an order of magnitude. The wafers with inhomogeneous defect distribution possess periodically patterned core-centers with higher defect density (up to 108 cm-2) than regions in between cores, which have very low defect concentrations (as low as 104 cm-2). The full width at 0.01 maximum of the triple axis rocking curves (GaN (0004)) shows a large variation ranging from 60 to 930 arcsec. In comparison, wafers without the periodic cores have a uniform defect density (~106 cm-2) and show a small variation in the rocking curve FW0.01M, ranging only from 70 to 280 arcsec. For Schottky diodes fabricated on substrate with cores, positioning the devices away from the core-centers results in a reduction of the reverse bias leakage by 2-4 orders of magnitude at -10 V. Similar trend are also observed in the p-i-n diodes, with device further away from the core-centers showing lower leakage. The devices in the low defect concentration region (> 200 um away from core centers) on the wafer with cores outperform the devices from the wafer without cores, showing up to 2 orders of magnitude lower leakage current at -200 V. The results from this study show that the substrate defect density and distribution play an important role on the device leakage current and avoiding highly defective regions on the substrate will improve the performance of vertical GaN devices.

Optimizing performance and yield of vertical GaN diodes using wafer scale optical techniques

To improve the manufacturing of vertical GaN devices for power electronics applications, the effects of defects in GaN substrates need to be better understood. Many non-destructive techniques including photoluminescence, Raman spectroscopy and optical profilometry, can be used to detect defects in the substrate and epitaxial layers. Raman spectroscopy was used to identify points of high crystal stress and non-uniform conductivity in a substrate, while optical profilometry was used to identify bumps and pits in a substrate which could cause catastrophic device failures. The effect of the defects was studied using vertical P-i-N diodes with a single zone junction termination extention (JTE) edge termination and isolation, which were formed via nitrogen implantation. Diodes were fabricated on and off of sample abnormalities to study their effects. From electrical measurements, it was discovered that the devices could consistently block voltages over 1000 V (near the theoretical value of the epitaxial layer design), and the forward bias behavior could consistently produce on-resistance below 2 mΩ cm2, which is an excellent value considering DC biasing was used and no substrate thinning was performed. It was found that high crystal stress increased the probability of device failure from 6 to 20%, while an inhomogeneous carrier concentration had little effect on reverse bias behavior, and slightly (~ 3%) increased the on-resistance (Ron). Optical profilometry was able to detect regions of high surface roughness, bumps, and pits; in which, the majority of the defects detected were benign. However a large bump in the termination region of the JTE or a deep pit can induce a low voltage catastrophic failure, and increased crystal stress detected by the Raman correlated to the optical profilometry with associated surface topography.

Using Wafer Scale Optical Profilometry to Estimate the Failure Rate of Vertical Pin GaN Diodes

GaN research is important to the development of next generation power conversion technology, for SiC based devices are limited to 13 kV loads, while GaN could theoretically handle 20 kV. Presently, commercialized GaN technology using lateral High Mobility Electron Transistors (HEMTs); however, vertical GaN devices could have 3 times larger critical electric field and a five order of magnitude lower dislocation density. Current GaN substrate manufacturing technology is known to produce inconsistent quality with a varying concentration of defects. These defects are known to cause catastrophic device failure, thus there is motive to develop quick, non-destructive techniques to predict the quality of the wafer before undergoing the expensive fabrication process. Our previous research [1,2], has studied several techniques to predict the quality of devices, and has correlated device quality to Raman spectroscopy data. This talk focuses on using optical profilometry data.Optical profilometry is a non-destructive technique capable of mapping the surface morphology of a whole wafer in a few hours. Since defects in the thin film or epitaxial layer often manifest themselves as abnormalities on the surface, this technique can be used to determine the regions of the sample where devices will fail. Dividing the samples into sub-regions, a generalized extreme studentized deviant test can be used to detect where outliers, which are likely defects, occur. From this, the location of the defects can be mapped and the probability of a devices landing on a defect can be calculated. Additionally, by knowing the location of the defects, they can be avoided thus increasing the device yield.This work was supported by the Office of Naval Research and ARPA-E OPEN+ Kilovolt Devices Cohort directed by Isik Kizilyalli.[1] J.C. Gallagher, T.J. Anderson, A.D. Koehler, M.A. Ebrish, G.M. Foster, M.A. Mastro, J.K. Hite, B.P. Gunning, R.J. Kaplar, K.D. Hobart, F.J. Kub, Effect of GaN Substrate Properties on Vertical GaN PiN Diode Electrical Performance, J. Electron. Mater. (2021). doi:10.1007/s11664-021-08840-9.[2] J.C. Gallagher, T.J. Anderson, L.E. Luna, A.D. Koehler, J.K. Hite, N.A. Mahadik, K.D. Hobart, F.J. Kub, Long range, non-destructive characterization of GaN substrates for power devices, J. Cryst. Growth. 506 (2019) 178–184. doi:10.1016/j.jcrysgro.2018.10.032.

(Invited) Vertical GaN Devices for High-Power Electronics

With the demand of high-power and high-speed electronics, GaN has achieved widespread interest owing to its wide-bandgap (WBG), large breakdown field, and high mobility that can provide superior performance compared to the Si and SiC that are limited by inherent material properties. In power electronics, GaN is a potential candidate due to its high-quality p-n junctions and availability of native substrates to prevent dislocation-assisted leakage, particularly for vertical devices. For high-power electronics, these vertical devices are more advantageous compared to their lateral counterparts due to their high current capability from large-area backside ohmic, high breakdown voltage from confined electric field within WBG material, scaling feasibility, and better thermal management. Moreover, the punch-through vertical device can extract the full potential of the WBG semiconductors by maximizing the average electric field over the fully depleted drift layer.For high-performance vertical device, high-quality drift layers with low controlled background doping and low compensating defects are essential to obtain the expected high breakdown voltage and low on-resistance. Hence, we have focused on both materials and device development for GaN power devices. Toward the first goal of high-quality GaN epitaxy, we optimized the growth condition for controlled low unintentionally doped (UID) and low impurity drift layer from ammonia molecular beam epitaxy (NH3 MBE). For this, we performed a systematic study of growth rate effects on the drift layer doping for a series of growth rates from 0.37 µm/hr to 1.68 µm/hr in both sapphire and free-standing GaN substrates (Fig. 1). A low background UID doping of ~1015 cm-3 was achieved with a growth rate 1.4 µm/hr on the free-standing GaN substrate. This UID background doping is one of the lowest reported for GaN homoepitaxy [1-3]. The potential of NH3 MBE-growth for low-doped epitaxy is recognized from our work, contributed from the cleaner growth environment of MBE, compared to the conventional metal-organic chemical vapor deposition (MOCVD).The next step of our work involved developing high-performance power devices with these high-quality epitaxies. Our vertical p-n GaN diode consisted of a ~4 µm UID GaN drift layer on ~0.25 µm of n+ GaN ([Si]: 1×1019 cm-3) buffer for the n-type region. The p-type region included a 10 nm p++ GaN cap ([Mg]: 3×1020 cm-3) to support the anode ohmic contact followed by a 0.4 µm p+GaN ([Mg]: 3×1019 cm-3) to form the p-n junction.The sample was fabricated with circular diodes of 80-100 µm diameter Pd/Pt Anode and a backside Ti/ Au Cathode. The field management was achieved by a combination of ~1.4 µm dry etch mesa isolation with a sidewall angle of ~55° and field plate (Fig. 2). For the field-plate dielectric, a stack of atomic layer deposition of Al2O3 (26 nm) and plasma-enhanced chemical vapor deposition of Si3N4 (205 nm) at 300 °C was used. Finally, a Ti/Pt metal stack of 15 µm length was patterned to form the field-plate.Capacitance-Voltage characteristics performed in these p-n diodes showed a doping of ~3×1015 cm-3 in the n- drift layer (Fig. 3a). Secondary ion mass spectrometry (SIMS) detected Si~2×1015 cm-3 and O ~2×1016 cm-3 respectively across the n-layer (Fig. 3b), likely the source of UID doping, accounting for their possible partial ionization. The compensating carbon impurities was less than the SIMS detection limit, certifying the high-quality NH3 MBE-growth. The forward J-V characteristics (Fig. 4) revealed the leakage current below the detection limit (~1.6 pA) for V<2 V. At higher forward biases (V=2.87 V) in the diffusion current region, the ideality factor reaches to a minimum of 1.36. The extracted specific on-resistance (Ron,sp) of 0.28 mΩ-cm2 and the minimum ideality factor of 1.36 are among the best achieved in vertical homoepitaxy GaN p-n diodes [1-3]. The highest breakdown voltage of these diodes were > 1 kV (equipment limit 1 kV) whereas some diodes exhibited breakdown at -890 V (Fig. 5). Silvaco simulation showed a punch-through breakdown of the diodes with peak electric field (EC) >2.6 MV/cm. Remarkably, this breakdown performance with NH3 MBE GaN of only ~4 um channel is comparable with the best available MOCVD GaN p-n diodes with a significantly thicker drift layer of ≥ 8 um (Fig. 6). Our work thus demonstrates the potential of high-performance power devices by NH3 MBE, benefitted from high-quality epitaxy, controlled low doping, and fast growth rates, that will be promising for high-voltage devices.

Surge Current and Avalanche Ruggedness of 1.2-kV Vertical GaN p-n Diodes

This letter reports the avalanche and surge current ruggedness of the industry's first 1.2-kV-class vertical GaN p-n diodes fabricated on 100-mm GaN substrates. The 1.2-kV vertical GaN p-n diodes with a 1.39-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> device area and an avalanche breakdown voltage of 1589 V show a critical avalanche energy density of 7.6 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in unclamped inductive switching tests, as well as a critical surge current of 54 A and a critical surge energy density of 180 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 10-ms surge current tests. All these values are the highest reported in vertical GaN devices and comparable to those of commercial SiC p-n diodes and merged p-n Schottky diodes. These GaN p-n diodes show significantly smaller reverse recovery compared to SiC p-n diodes, revealing less conductivity modulation in n-GaN. The negative temperature coefficient of differential on-resistance and the anticlockwise surge <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I–V</i> locus are believed to be due to the increased acceptor ionization in p-GaN and the decreased contact resistance at high temperatures. These results suggest a high ruggedness of GaN p-n junctions with small bipolar currents and fast switching capabilities. As the first electrothermal ruggedness data for industry's vertical GaN devices, these results provide key new insights for the development of vertical GaN devices as well as their application spaces.

Floral design GaN crystals: low-resistive and low-dislocation-density growth by oxide vapor phase epitaxy

GaN crystal growth mode in the oxide vapor phase epitaxy (OVPE) method, which simultaneously provides low electrical resistance and low threading dislocation density (TDD), has been investigated in detail. The results clarified that these qualities can be achieved by the expression of numerous inverted pyramidal pits, called three-dimensional (3D) growth mode. This mode reduced TDD from 3.8 × 106 cm−2 to 2.0 × 104 cm−2 for 1 mm thick growth because the threading dislocations (TDs) converged to the center of each pit. Moreover, when the crystal surface after polishing was observed by photoluminescence measurement, peculiar floral designs reflecting the distribution of oxygen concentration were observed over the entire surface. In addition, the etch pits exhibited TDs in the center of each floral design. On the basis of our results, we proposed that the 3D-OVPE-GaN will serve as a key material for improving the performance of vertical GaN devices.