Vertex Tracker Research Articles

Advances in the development of pixel detector for the SuperB Silicon Vertex Tracker

The latest advances in the design and characterization of several pixel sensors developed to satisfy the very demanding requirements of the innermost layer of the SuperB Silicon Vertex Tracker will be presented in this paper. The SuperB machine is an electron positron collider operating at the ϒ(4S) peak to be built in the very near future by the Cabibbo Lab consortium. A pixel detector based on extremely thin, radiation hard devices able to cope with rate in the tens of MHz/cm2 range will be the optimal solution for the upgrade of the inner layer of the SuperB tracking system. At present several options with different levels of maturity are being investigated to understand advantages and potential issues of the different technologies: thin hybrid pixels, Deep N-Well CMOS MAPS, INMAPS CMOS MAPS featuring a quadruple well and high resistivity substrates and CMOS MAPS realized with Vertical Integration technology. The newest results from beam test, the outcomes of the radiation damage studies and the laboratory characterization of the latest prototypes will be reported.

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R&D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

Higher harmonics flow measurement of charged hadrons and electrons in wide kinematic range with PHENIX VTX tracker

The silicon vertex tracker (VTX) was installed into the PHENIX experiment in 2010 and it successfully collected approximately 5 billion events of Au + Au collisions at 200 GeV in the 2011 RHIC run. The main function of the VTX is separation of heavy flavor hadrons, charm and bottom, with a measurement of Distance of Closest Approach (DCA) of single electrons from heavy flavor decays. By identifying electrons with PHENIX central detectors, the azimuthal anisotropy of electrons from heavy flavor decays can be determined over a broad p T range. In this paper, we will present measurement results on v 2 and v 3 of charged hadrons, and v 2 of single electron from charm decay.

Probing Hot and Dense Matter with Charm and Bottom Measurements with PHENIX VTX Tracker

We present the first measurements of the nuclear modification factor ( R A A ) for flavor-separated b , c -quark electrons in Au + Au collisions at s N N = 200 GeV . The newly installed Silicon Vertex Tracker is used to measure the distance of closest approach distributions of electrons at midrapidity ( | η | < 0.35 ) over the transverse momentum range 1 < p T e < 5 GeV / c . From this, the relative fraction of bottom ( b ) and charm ( c ) quarks is determined in both the p + p and Au + Au collision systems, which form the basis of the measured R A A . In p + p , we observe that a FONLL perturbative QCD calculation of b → e / ( c → e + b → e ) ratio is in good agreement with the data. In Au + Au, the data imply a large suppression of b → e or a large modification of B meson p T distributions, which implies very interesting physics of B mesons in Au + Au collisions.

Heavy Flavor Physics in PHENIX

Heavy quarks are good probes of the hot and dense medium created in relativistic heavy ion collisions since they are mainly generated early in the collision and interact with the medium in all collision stages. In addition, heavy flavor quarkonia production is thought to be uniquely sensitive to the deconfined medium of the Quark Gluon Plasma (QGP) through color screening. Heavy quark production has been studied by the PHENIX experiment at RHIC via measurements of single leptons from semi-leptonic decays, in both the electron channel at mid-rapidity and in the muon channel at forward rapidity. Large suppression and azimuthal anisotropy of single electrons have been observed in Au+Au collisions at GeV. These results suggest a large energy loss and strong flow of the heavy quarks in the hot, dense matter. The PHENIX experiment has also measured J/ψ production in p + p, d+Au, Cu+Cu, and Au+Au collisions at energies up to GeV. In central Au+Au at 200 GeV, more suppression is observed at forward rapidity than at central rapidity. This can be interpreted either as a sign of quark recombination, or as a hint of additional cold nuclear matter effects. Selected PHENIX results on open heavy flavor and heavy quarkonia production in p + p, d + Au, Cu+Cu, and Au+Au collisions are presented. The status of the recent PHENIX upgrade of the central Silicon Vertex Tracker (VTX) and its performance are elucidated.

The P̄ANDA MVD silicon strip detector

The P̄ANDA experiment at the future FAIR facility will study annihilation reactions of antiprotons. The Micro-Vertex-Detector (MVD) as part of the tracking system will permit precise tracking and detection of secondary vertices. It is made of silicon pixel detectors and double-sided silicon strip detectors.The unique data acquisition concept without a central trigger poses a challenge to all sub-detectors.Developments for the MVD strip detector cover the evaluation of prototype sensors as well as the readout chain, ranging from the front-end for the trigger-less readout over the Module Data Concentrator ASIC to the off-detector electronics.

A quadruple well CMOS MAPS prototype for the Layer0 of the SuperB SVT

The chip prototype Apsel4well, including monolithic active pixel sensors (MAPS), is meant as an upgrade solution for the Layer0 of the SuperB silicon vertex tracker. The design is based on a 180nm CMOS process with quadruple well called INMAPS. This technology makes it possible to overcome the main drawbacks of three transistor MAPS. Moreover, the presence of a high resistivity epitaxial layer is expected to lead to a further improvement in terms of charge collection performance and radiation resistance. This work introduces the channel readout design features of the chip Apsel4well developed with the mentioned approach and shows results of device simulations of a 3×3 pixel matrix.

Analog front-end electronics for the outer layers of the SuperB SVT: Design and expected performances

The Silicon Vertex Tracker (SVT) of the new SuperB collider will be composed of 6 different detector layers [1]. The innermost layer (L0) will be composed by striplets or pixels [2]; the other 5 detector layers will be double-sided long-strip detectors. The strip geometries and the foreseen hit-rates will change according to the different layers. As a consequence, different optimization of the analog read-out electronics is needed in order to provide high detection-efficiency and low noise level in the different layers. Two readout ASICs are currently developed, one for layers 0–3, another for layers 4 and 5; they differ mainly in the analog front-end.In this work, we present the design and the expected performances of the analog front-end for layers 4 and 5. For these layers, the strip detectors show a very high stray capacitance and high series resistance. In this condition, the noise optimization is our primary concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been found. We will present the design of preamplifier and shaper and the results of simulation of noise performance and efficiency (with the expected background rates). In addition, the design of the time-over-threshold and its use to correct the time-walk of the event trigger is discussed as well as the achievable timing accuracy of the circuit.

The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT

Six layers of microstrip detectors are foreseen in the present baseline design of the SuperB Silicon Vertex Tracker. Different strip pitches and lengths will be used in the various SVT layers; however, the capability of standing a high background rate and of operating with high hit detection efficiency will be a common feature of the innermost layers. These requirements set the need for a readout chip with analog channels with a short signal shaping time (25–200ns in layers 0–3) to achieve an adequate time stamp resolution and a small pulse overlap. These channels are also required to provide a 4-bit hit amplitude resolution for dE/dx measurements. A new chip is being designed in a 130nm CMOS process to comply with these specifications. This paper discusses the solutions that are adopted in this chip for the various blocks of the analog channels, and will present the simulation results for the current design along with the expected performance in terms of parameters such as signal-to-noise ratio, dynamic range, linearity, power dissipation.

The front-end chip of the SuperB SVT detector

The asymmetric e+e− collider SuperB is designed to deliver a high luminosity, greater than 1036cm−2s−1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2MHz per strip, the efficiency of the digital readout remained above 99.8%.

A beam radiation monitor based on CVD diamonds for SuperB

Chemical Vapor Deposition (CVD) diamond particle detectors are in use in the CERN experiments at LHC and at particle accelerator laboratories in Europe, USA and Japan mainly as beam monitors. Nowadays it is considered a proven technology with a very fast signal read-out and a very high radiation tolerance suitable for measurements in high radiation environment zones i.e. near the accelerators beam pipes. The specific properties of CVD diamonds make them a prime candidate for measuring single particles as well as high-intensity particle cascades, for timing measurements on the sub-nanosecond scale and for beam protection systems in hostile environments.A single-crystalline CVD (scCVD) diamond sensor, read out with a new generation of fast and high transition frequency SiGe bipolar transistor amplifiers, has been tested for an application as radiation monitor to safeguard the silicon vertex tracker in the SuperB detector from excessive radiation damage, cumulative dose and instantaneous dose rates. Test results with 5.5MeV alpha particles from a 241Am radioactive source and from electrons from a 90Sr radioactive source are presented in this paper.

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5cm), resolution of 10–15μm in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180nm process and the 130nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

Beam test results for the SuperB-SVT thin striplet detector

The baseline detector option for the first layer of the SuperB Silicon Vertex Tracker (SVT) is a high resistivity double-sided silicon device with short strips (striplets) at 45° angle to the detector's edge. A prototype was tested with a 120GeV/c pion beam in September 2011 at the SPS-H6 test-beam line at CERN. In this paper studies on efficiency, resolution and cluster size are reported.

Characterization of strip detector parameters for the SuperB Silicon Vertex Tracker

The Silicon Vertex Tracker for the SuperB detector is designed as an evolution of the BaBar SVT, based on double-sided strip detectors. The wider acceptance in polar angle (down to 300 milliradians) will imply larger incidence angles (up to 73°) on the sensors. On the z-side (reading out the z coordinate, along the beam direction) this results in large clusters with small signal values on individual channels. For optimum performance it would be desirable to continuously vary the sensor pitch on z-side versus position. An easy and convenient way to approximate this configuration is to bond two or three adjacent strips to a single trace of the fanout circuit that connects the strips to the front-end electronics (the so-called ‘pairing’ option). In order to accurately measure the total capacitance of strips in various pairing configurations (×2,×3,×4) two test detectors have been assembled on PCBs, and various strip connection schemes have been implemented by wire bonding, on p and on n-side, respectively. Capacitance and dissipation factor have been measured versus bias voltage and frequency. These data are being used to estimate the noise contribution of the detector and to choose the best z-side connection scheme in the SVT.

The calculation of the speed performance of the CLAS12 silicon vertex tracker

The CLAS12 experiment is intended to study the generalized parton distributions in exclusive reactions. The CLAS12 Silicon Vertex Tracker must provide the registration of all reaction products at the expected high luminosity. The results of a GEANT4 simulation of the expected physical rates in the SVT are presented. The frequency of the noise hits of the readout electronics is determined on the basis of the capacitive load generated by the attached sensors. In order to find the fraction of the events that are lost due to delays in the readout electronics, a computer simulation of the logic of the data-driven readout FSSR2 chip is performed. At a signal-to-noise ratio of 8 to 1 the readout electronics are capable of processing the expected rates, provided a registration threshold of 0.4 mip is preset.

Studies of vertex tracking with SOI pixel sensors for future lepton colliders

This paper presents a study of vertex tracking with a beam hodoscope consisting of three layers of monolithic pixel sensors in SOI technology on high-resistivity substrate. We study the track extrapolation accuracy, two-track separation and vertex reconstruction accuracy in π− Cu interactions with 150 and 300GeV/c pions at the CERN SPS. Results are discussed in the context of vertex tracking at future lepton colliders.

Optimum Design of DACs for Threshold Correction in Multichannel Processors for Radiation Detectors

This work is intended to provide a set of guidelines for the design of digital-to-analog converters enabling the reduction of threshold dispersion in multichannel readout circuits for radiation detectors. The design criteria are first established through a theoretical approach and then confirmed by means of a simulation tool based on Monte Carlo methods. This latter tool provides a fast and flexible way to predict the performance of a DAC for threshold correction, also accounting for possible non-idealities, such as differential and integral non linearities and gain and offset errors. The proposed guidelines have been validated through simulations on front-end circuits for a real application, the silicon vertex tracker for the SuperB Factory, and through comparison with data available in the literature.

Advanced Pixel Sensors and Readout Electronics Based on 3D Integration for the SuperB Silicon Vertex Tracker

The potential of 3D integration of sensors and readout electronics is being explored in view of the demanding requirements of the innermost layer of the SuperB Silicon Vertex Tracker. This paper reviews the 3D designs that are targeting SuperB, which include CMOS active pixel sensors and front-end chips for fully-depleted, high-resistivity pixel sensors.

Forward Silicon Vertex Tracker for the PHENIX experiment at RHIC

The PHENIX experiment at RHIC is well in the process of constructing a silicon vertex tracker consisting of a central barrel component (already undergoing commissioning), as well as two forward rapidity components. This report gives an overview of the physics goals of the forward vertex tracker (FVTX), and gives the current status of its construction. It is scheduled to be completed this year and commissioned during the next RHIC run.

Discharge rate measurements for Micromegas detectors in the presence of a longitudinal magnetic field

We present first discharge rate measurements for Micromegas detectors in the presence of a high longitudinal magnetic field in the GeV kinematical region. Measurements were performed by using two Micromegas detectors and a photon beam impinging a CH{sub 2} target in the Hall B of the Jefferson Laboratory. One detector was equipped with an additional GEM foil, and a reduction of the discharge probability by two orders of magnitude compared to the stand-alone Micromegas was observed. The detectors were p laced in the FROST solenoid providing a longitudinal magnetic field up to 5T. It allowed for precise measurements of the discharge probability dependence with a diffusion-reducing magnetic field. Between 0 and 5T, the discharge probability increased by a factor of 10 for polar angles between 19{degrees} and 34{degrees}. A GEANT4-based simulation developed for sparking rate calculation was calibrated against these data in order to predict the sparking rate in a high longitudinal magnetic field environment. This simulati on is then used to investigate the possible use of Micromegas in the Forward Vertex Tracker (FVT) of the future CLAS12 spectrometer. In the case of the FVT a sparking rate of 1Hz per detector was obtained at the anticipated CLAS12 luminosity.