Verilog Simulation Research Articles

Cryo-CMOS Multi-Frequency Modulator for 2-Qubit Controller

This paper addresses the design of a CMOS modulator to control two quantum bits. The proposed architecture offers several advantages that are addressed and discussed in this paper. The proposed architecture is investigated through both mathematical modeling and Verilog simulations. Moreover, the circuit was designed using the cryogenic Design Kit of the 130 nm SiGe BiCMOS technology of the IHP foundry. The observed agreement between the modeling, Verilog, and transistor-level simulations proves the physical feasibility of the proposed architecture.

Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers

Fault attacks pose a potent threat to modern cryptographic implementations, particularly those used in physically approachable embedded devices in IoT environments. Information security in such resource-constrained devices is ensured using lightweight ciphers, where combinational circuit implementations of SBox are preferable over look-up tables as they are more efficient regarding area, power, and memory requirements. Most existing fault analysis techniques focus on fault injection in memory cells and registers. Recently, a novel fault model and analysis technique, namelySemi-Permanent Stuck-At(SPSA) fault analysis, has been proposed to evaluate the security of ciphers with combinational circuit implementation ofSubstitution layerelements, SBox. In this work, we propose optimized techniques to recover the key in a minimum number of ciphertexts in such implementations of lightweight ciphers. Based on the proposed techniques, a key recovery attack on the NIST lightweight cryptography (NIST-LWC) standardization process finalist,ElephantAEAD, has been proposed. The proposed key recovery attack is validated on two versions ofElephantcipher. The proposed fault analysis approach recovered the secret key within 85–240 ciphertexts, calculated over 1,000 attack instances. To the best of our knowledge, this is the first work on fault analysis attacks on theElephantscheme. Furthermore, an optimized combinational circuit implementation ofSpongentSBox (SBox used inElephantcipher) is proposed, having a smaller gate count than the optimized implementation reported in the literature. The proposed fault analysis techniques are validated on primary and optimized versions ofSpongentSBox through Verilog simulations. Further, we pinpoint SPSA hotspots in the lightweightGIFTcipher SBox architecture. We observe thatGIFTSBox exhibits resilience toward the proposed SPSA fault analysis technique under the single fault adversarial model. However,eightSPSA fault patterns reduce the nonlinearity of the SBox to zero, rendering it vulnerable to linear cryptanalysis. Conclusively, SPSA faults may adversely affect the cryptographic properties of an SBox, thereby leading to trivial key recovery. TheGIFTcipher is used as an example to focus on two aspects: (i) its SBox construction is resilient to the proposed SPSA analysis and therefore characterizing such constructions for SPSA resilience and (ii) an SBox even though resilient to the proposed SPSA analysis, may exhibit vulnerabilities toward other classical analysis techniques when subjected to SPSA faults. Our work reports new vulnerabilities in fault analysis in the combinational circuit implementations of cryptographic protocols.

64-GHz Operation of the Pseudorandom Binary Sequence Generator Using the Dual RSFQ/ERSFQ Standard Cell Library

A pseudo-random binary sequence of 7-bit word length (PRBS-7) generator has been designed as a low complexity circuit to validate the dual RSFQ/ERSFQ standard cell library, the circuit simulation methodology using process corners and Monte-Carlo statistical variations, as well as the digital design methodology using Verilog simulations with load-dependent timing back-annotation. The PRBS-7 design was optimized across multiple process corners with Monte-Carlo circuit simulations by incorporating statistical variations of the process parameters. To validate the digital design flow, the PRBS-7 was simulated using the Verilog behavioral descriptions of library cells. Using Liberty files for different global bias current (XI) process corners, the margins obtained from digital simulation were compared with circuit simulations. A 5 mm × 5 mm chip, incorporating both, the RSFQ and ERSFQ variant of the PRBS-7, was fabricated in the MIT-LL 100 μA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fab node. The RSFQ variant of the PRBS-7 has been successfully tested up to 64.77 GHz clock frequency, and the ERSFQ variant up to 45.72 GHz clock frequency. In addition, we have analyzed the model-to-hardware correlation for RSFQ PRBS-7 for different clock frequencies. The simulations account for two process parameters, critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_s</i> ).

Secure double MAC implementation for STBC based FECG monitoring

One of the best methods for assessing a baby’s health is foetal electrocardiography (FECG). Previously restricted to more widespread global disorders such as common ischemia, it is new way to investigating foetal heart rate irregularities. Current prenatal monitoring practices ignore critical FECG waveform elements that are the foundation of both pediatric, adult cardiac assessment, and instead of focusing solely on the foetal heart rate. In this paper we proposed Double Multiply-and-Accumulate (MAC) approach used for package operators into a single DSP block of commercial FPGAs, theoretically doubling the calculation speed for FECG monitoring. For a variety of technical reasons, they were using the Space-Time Block Code (STBC) monitoring mode of operation. To strengthen the security of FECG monitoring, the Advanced Encryption Standard (AES) method may be used with the double MAC operators using STBC based FECG monitoring that has been developed. The solution was then assessed using state-of-the-art the Space-Time Block Code (STBC) based FECG techniques, and its validity was confirmed using Verilog simulation and FPGA synthesis. The calculation throughput of an STBC-based FECG monitoring system was found to be doubled using the Double MAC approach. Our implementation result demonstrates that keys are necessary for 128-bit AES encoding and decoding operations via VHDL-coded transformations. It is now more vital than ever to do a feasibility analysis of any hardware design due to the increase in the number of ways presented for minimizing noise. The efficiency increased (92%), and the delay was decreased to 19.35 ns by employing this double MAC architecture. The simulation results demonstrate that transformations for coding on an FPGA are implemented using the Xilinx VIVADO tool.

RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool

DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems. DEVS provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend the RTL-DEVS model based on DEVS formalism to enable part of Verilog simulation in DEVS-based simulation tools. The simulation based on RTL-DEVS methodology, which imitates Verilog’s testbench and behavioral module, confirmed through experiments that RTL simulation can be performed sufficiently through the code elaboration process. In multiple simulation results, Verilog simulation and RTL-DEVS-based simulation were able to output equivalent results under limited conditions. DEVS formalism-based modeling can be extended to other DEVS-based simulators when using model-type exchange tools, and this means that the advanced functions or classes of RTL simulation tools can be applied using higher-level language tools.

Efficient hardware realization and high radix implementation of modular multi exponential techniques for public key cryptography

Modular multi exponentiation (MME) is a critical operation in most of the public-key cryptosystems and verification functions. Two novel algorithms: HRMME and SFWHRMME, are proposed to evaluate the MME efficiently. The evaluation process of the proposed algorithm has an inbuilt confusion mechanism, which increases the security level. The side-channel attacks and timing attacks are counteracted by algorithmic means instead of using only hardware measures. The high-radix implementation is efficiently reducing the required number of clock cycles. The performance of the proposed algorithms is analyzed in terms of power, throughput and energy. The experimental results show that the proposed techniques HRMME and SFWHRMME increase the throughput in the order of 23.55% and 23.67%, respectively and consume less power in the order of 21.78% and 21.88%. Xilinx Vivado 21.2 on Virtex-7 evaluation boards and ICARUS Verilog simulation & synthesis tools are used for FPGA for hardware realization. The hardware compatibility of proposed algorithms has also been checked using Cadence for ASIC.

A parallel hardware hypervisor for hardware‐accelerated cloud computing

SummaryHardware‐accelerated cloud computing systems based on FPGA or ASIC chips have proved useful in providing power‐efficient acceleration for a variety of software applications. However, these computing systems rely on operating systems and hypervisors, which not only are implemented with inefficient software, but which also are incapable of handling massively parallel systems, due to the lack of parallelism and scalability in their algorithmic designs. As a result, power, performance, and scalability problems will emerge in an exascale cloud computing environment. As a solution to these problems, the present study proposes a parallel hardware hypervisor system implemented entirely in special‐purpose hardware without resorting to energy‐inefficient general‐purpose processors. Furthermore, the proposed hypervisor system virtualizes application‐specific multi‐chip supercomputers, in order to enable the virtual supercomputers to share available FPGA and semi‐configurable ASIC resources in a cloud system. Single‐chip verification studies based on Verilog simulation have been done to verify the functional correctness of the proposed hardware hypervisor system, which consumes only a fraction of hardware resources. This article will in particular focus on the virtualization of multi‐chip message‐passing based supercomputers using limited reconfigurable hardware resources.

Hardware Acceleration of the STRIKE String Kernel Algorithm for Estimating Protein to Protein Interactions

Protein-protein interaction (PPI) is an important field in bioinformatics which helps in understanding diseases and devising therapy. PPI aims at estimating the similarity of protein sequences and their common regions. STRIKE was introduced as a PPI algorithm which was able to achieve reasonable improvement over existing PPI prediction methods. Although it consumes a lower execution time than most of other state-of the-art PPI prediction methods, its compute-intensive nature and the large volume of protein sequences in protein databases necessitate further time acceleration. In this paper, we develop hardware accelerator designs for the STRIKE algorithm. Results indicate that the weighted STRIKE accelerator execution times are about 10x longer than the unweighted STRIKE accelerator execution times. To further accelerate the performance of the weighted STRIKE, a parallel module accelerator organization duplicating the weighted STRIKE modules is introduced, achieving near linear speedups for long sequences of 100 or more characters. As demonstrated by Verilog simulations and FPGA runs, the weighted STRIKE module accelerator exhibits three orders of magnitude speed improvement over multi-core and cluster computers. Much higher speedups are possible with the parallel module accelerator.

Fast Validation of Mixed-Signal SoCs

Today’s mixed-signal SoCs are challenging to validate. Running enough test vectors often requires the use of event-driven simulation and hardware emulation, which in turn necessitates the creation of analog behavioral models. This paper reviews different approaches proposed to address that modeling challenge, and shows how they can be divided by the methods used to solve for analog circuit values, represent analog waveforms, and validate analog functional models. We illustrate the power of these techniques as applied to a 16 Gb/s PHY, demonstrating a 10, $000\times $ speedup vs. SPICE simulation using event-driven models in Verilog simulation, and a further 5, $000\times $ speedup using synthesizable analog models in FPGA emulation.

RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining

RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. The processor applies three effective optimization methods to improve the operating frequency. These methods are instruction fetch unit optimization including pipelined branch prediction mechanism, ALU optimization, and data alignment and sign-extension optimization for data memory output. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.

Multi Fluxon Storage and its Implications for Microprocessor Design

One of the main challenges for single flux quantum (SFQ) technology to successfully implement a microprocessor is to have a compact and robust on-chip memory that can be used for register files and cache memory. In this context, we designed high capacity destructive readout (HC-DRO) cells. The design is based on our insight that each cell can store more than one SFQ pulse with the same area footprint of a regular DRO cell. In our current design, we demonstrate a single HC-DRO cell that can store up to three SFQ pulses thereby enabling us to store the equivalent of two bits of memory in a single cell. We have designed a register file (RF) architecture for a microprocessor and used the HC-DRO cells to reduce the Josephson junction count required for its implementation. The RF architecture presented in this work can also be used for implementing cache memories. We also demonstrate the benefits of doubling the storage density with HC-DRO cells by designing a 2-bit branch predictor circuit block for a 5-stage pipeline microprocessor that dramatically improves the cycles per instruction metric of an SFQ based microprocessor. All the design details are presented in the paper by verifying the design concepts through JSIM simulations and Verilog simulations.

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol

The risk of soft errors due to radiation continues to be a significant challenge for engineers trying to build systems that can handle harsh environments. Building systems that are Radiation Hardened by Design (RHBD) is the preferred approach, but existing techniques are expensive in terms of performance, power, and/or area. This paper introduces a novel soft-error resilient asynchronous bundled-data design template, SERAD, which uses a combination of temporal and spatial redundancy to mitigate Single Event Transients (SETs) and upsets (SEUs). SERAD uses Error Detecting Logic (EDL) to detect SETs at the inputs of sequential elements and correct them via re-sampling. Because SERAD only pays the delay penalty in the presence of an SET, which rarely occurs, its average performance is comparable to the baseline synchronous design. We tested the SERAD design using a combination of Spice and Verilog simulations and evaluated its impact on area, frequency, and power on an open-core MIPS-like processor using a NCSU 45nm cell library. Our post-synthesis results show that the SERAD design consumes less than half of the area of the Triple Modular Redundancy (TMR), exhibits significantly less performance degradation than Glitch Filtering (GF), and consumes no more total power than the baseline unhardened design.

A study of the nonlinear dynamics of human behavior and its digital hardware implementation

This paper introduces an intensive discussion for the dynamical model of the love triangle in both integer and fractional-order domains. Three different types of nonlinearities soft, hard, and mixed between soft and hard, are used in this study. MATLAB numerical simulations for the different three categories are presented. Also, a discussion for how the kind of personalities affects the behavior of chaotic attractors is introduced. This paper suggests some explanations for the complex love relationships depending on the impact of memory (IoM) principle. Lyapunov exponents, Kaplan-Yorke dimension, and bifurcation diagrams for three different integer-order cases show a significant dependency on system parameters. Hardware digital realization of the system is done using the Xilinx Artix-7 XC7A100T FPGA kit. Version 14.7 from the Xilinx ISE platform is used in both Verilog simulation and hardware implementation stages. The digital approach of such a system opens the door to predict the love relation after sensing the human personality. Also, this study will help in justifying more human emotions like happiness, panic, and fear accurately. Perhaps shortly, this study may combine with artificial intelligence to demonstrate Human-Computer interaction products.

Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations

Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.

Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs

Deep learning workloads, such as convolutional neural networks (CNNs) are important due to increasingly demanding high-performance hardware acceleration. One distinguishing feature of a deep learning workload is that it is inherently resilient to small numerical errors and thus works very well with low precision hardware. We propose a novel method called double multiply-and-accumulate (MAC) to theoretically double the computation rate of CNN accelerators by packing two MAC operations into one digital signal processing block of off-the-shelf field-programmable gate arrays (FPGAs). We overcame several technical challenges by exploiting the mode of operation in the CNN accelerator. We have validated our method through FPGA synthesis and Verilog simulation, and evaluated our method by applying it to the state-of-the-art CNN accelerator. The double MAC approach used can double the computation throughput of a CNN layer. On the network level (all convolution layers combined), the performance improvement varies depending on the CNN application and FPGA size, from 14% to more than 80% over a highly optimized state-of-the-art accelerator solution, without sacrificing the output quality significantly.

Design and Implementation of High-Speed Variable Point Pipelined FFT Processor for OFDM System using Verilog

Objectives: For Orthogonal Frequency Division Multiplexing (OFDM), Fast Fourier Transform (FFT) processoris required. So, in this work, a variable point Pipelined FFT processor is designed by utilizing Verilog language. Further transmitter and receiver blocks are designed to form OFDM system. Methods: Speed enhancement is the key area which is been looked into this project work. Pipelined Architecture that is going to be implemented is RS2DF (Radix-2 Single path Delay Feedback). Standard FPGA Flow is adapted to implement this project i.e., right from specification to bit file generation. Simulations and Synthesis will be done using Questasim and Xilinx ISE. Verilog Simulations will be compared with in-built MATLAB FFT Core. MATLAB is used for reference and verification. Findings: This Project clarified the usage of FFT IP and OFDM in Xilinx ISE focusing on a specific family of FPGA. The execution of the proposed algorithm ought to perform superior to anything the base algorithm with the all-out basic way getting additionally advanced along these lines expanding the speed of activity. maximum operation frequency achieved was 236.189MHz but in base paper maximum operation frequency was 30Mhz. The systems utilized are Interna1 and externa1 Pipe1ining of modules and Distributed LUT based idea, the target of the above methods is to lessen the basic way deferral and increment the general speed of activity of structure, the disadvantage is the increments in area and output latency. Area is not of a much issue as present day days FPGAs has immense measure of assets. Output 1atency should be taken consideration with additional rationale at whatever point FFT is coordinated with other system modules. Application: The project depicts technique for streamlining timing basic ways of FFT to work at higher-speeds, to be utilized as a feature of LTE Protoca1 or any wire1ess protoco1 such as WLAN and LDACS. Keywords: Fast Fourier Transform (FFT), Hardware Description Language (HDL), Orthogonal Frequency Division Multiplexing (OFDM), Pipeline, Verilog

Hardware-assisted Verilog simulation system using an application specific microprocessor

Verilog is a Hardware Description Language (HDL) used for VLSI design and modeling. A software-based Verilog simulator running on general purpose computer is the dominant simulation platform. However, the platform is throughput limited at simulating next generation designs. Commercial hardware-assisted solutions are proprietary with various limitations. A hardware-assisted platform through the use of an application specific simulation processor is proposed in this paper. Program flow of this processor is driven by HDL simulation semantics. The microprocessor is customized to support Verilog operations with computation using the language's native data types (0, 1, X, Z) from behavioral to gate-level abstraction, including delay and signal strength modeling. Besides, fine-grained parallel event dispatch and hardware-augmented netlist traversing are acceleration features built in the microprocessor. A prototype was built on an FPGA to demonstrate system viability. Benchmarking against a software-based compiled-code simulator had shown up to 9 times simulation time improvement despite having limited basic speed improvement techniques implemented. Capacity scalability can be achieved through parallel processing and memory expansion. The system offers speed improvement over software-based simulator, while retaining the same usability. These leave unbounded room of improvements to meet future simulation needs.

Acceleration of Simulated Fault Injection Using a Checkpoint Forwarding Technique

Simulated fault injection (SFI) is widely used to assess the effectiveness of fault tolerance mechanisms in safety-critical embedded systems (SCESs) because of its advantages such as controllability and observability. However, the long test time of SFI due to the large number of test cases and the complex simulation models of modern SCESs has been identified as a limiting factor. We present a method that can accelerate an SFI tool using a checkpoint forwarding (CF) technique. To evaluate the performance of CF-based SFI (CF-SFI), we have developed a CF mechanism using Verilog fault-injection tools and two systems under test (SUT): a single-core-based co-simulation model and a triple modular redundant co-simulation model. Both systems use the Verilog simulation model of the OpenRISC 1200 processor and can execute the embedded benchmarks from MiBench. We investigate the effectiveness of the CF mechanism and evaluate the two SUTs by measuring the test time as well as the failure rates. Compared to the SFI with no CF mechanism, the proposed CF-SFI approach reduces the test time of the two SUTs by 29%–45%.

Energy efficient modular exponentiation for public-key cryptography based on bit forwarding techniques

Modular exponentiation and modular multiplications are two fundamental operations in various cryptographic applications, and hence the performance of public-key cryptographic algorithms is strongly influenced by the efficient implementation of these operations. Reducing the frequency of modular multiplications and the time requirements for modular multiplication will help in developing efficient modular exponential algorithms. This work proposes an energy efficient modular exponential algorithm based on bit forwarding techniques. In particular, two algorithms, Bit Forwarding 1-bit (BFW1) and Bit Forwarding 2-bits (BFW2), which are modifications of the existing binary exponential algorithm, have been developed. Hardware realizations of the proposed algorithms have been evaluated in terms of throughput, power and energy. Results show increased throughput of the order of 11.02% and 15.13%, reduction in power to 1.93% and 6.35% and energy saving of the order of 1.9% and 6.35% for BFW1 and BFW2 algorithms respectively. Xilinx ISE-14.2 on Virtex-5 evaluation board and ICARUS verilog simulation and synthesis tool are used for hardware realization for FPGA and synthesized using Cadence for ASIC.

Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.