RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool

Abstract

DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems. DEVS provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend the RTL-DEVS model based on DEVS formalism to enable part of Verilog simulation in DEVS-based simulation tools. The simulation based on RTL-DEVS methodology, which imitates Verilog’s testbench and behavioral module, confirmed through experiments that RTL simulation can be performed sufficiently through the code elaboration process. In multiple simulation results, Verilog simulation and RTL-DEVS-based simulation were able to output equivalent results under limited conditions. DEVS formalism-based modeling can be extended to other DEVS-based simulators when using model-type exchange tools, and this means that the advanced functions or classes of RTL simulation tools can be applied using higher-level language tools.