Discrete event system specification, synthesis, and optimization of low-power FPGA-based embedded systems

Abstract

Discrete event system specification (DEVS) has been widely used within modeling and simulation to design, verify, and implement complex reactive systems. DEVS provides a robust formalism for designing systems using event-driven, state-based models in which timing information is explicitly defined. In this paper, we present an overview of a DEVS-based hardware design, synthesis, and optimization methodology. Within this approach, hardware DEVS (HDEVS) specifications can be synthesized to hardware, during which the event-driven model and explicit timing allow for an efficient hardware realization using globally asynchronous, locally synchronous design approach. Additionally, we present an optimization method for reducing power consumption through optimal frequency mapping and clock gating of individual components while ensuring system latency constraints are achieved. We further demonstrate the resulting power consumption savings for activity-driven forest fire and asthma health management applications targeting two low-power FPGA devices.