Hardware-assisted Verilog simulation system using an application specific microprocessor

Abstract

Verilog is a Hardware Description Language (HDL) used for VLSI design and modeling. A software-based Verilog simulator running on general purpose computer is the dominant simulation platform. However, the platform is throughput limited at simulating next generation designs. Commercial hardware-assisted solutions are proprietary with various limitations. A hardware-assisted platform through the use of an application specific simulation processor is proposed in this paper. Program flow of this processor is driven by HDL simulation semantics. The microprocessor is customized to support Verilog operations with computation using the language's native data types (0, 1, X, Z) from behavioral to gate-level abstraction, including delay and signal strength modeling. Besides, fine-grained parallel event dispatch and hardware-augmented netlist traversing are acceleration features built in the microprocessor. A prototype was built on an FPGA to demonstrate system viability. Benchmarking against a software-based compiled-code simulator had shown up to 9 times simulation time improvement despite having limited basic speed improvement techniques implemented. Capacity scalability can be achieved through parallel processing and memory expansion. The system offers speed improvement over software-based simulator, while retaining the same usability. These leave unbounded room of improvements to meet future simulation needs.