SoC Verification Research Articles

Практика и перспективы применения открытых и собственных программных решений в маршруте верификации систем на кристалле

This article discusses the experience and evaluates the capability of using free, open and internal proprietary EDA tools in the billon gates SoC verification flow initially based on the commercial EDA of the “Big 3”. Article suggests an approach to assessing the suitability of a particular EDA tools for a certain stage of the verification flow based on a formal stage description and requirements for the tool. It presents our internal tools implemented in the company, which are used as an alternative to commercial tools or as unique solutions. Based on the proposed approach, the analysis of the existing automation tools from the point of view of the applicability in the SoC verification flow was carried out.

RISC-V SOC Verification

RISC-V SOC Verification

Continuous Verification

JOHN HAMMAN looks at continuous SoC verification from pre-fabrication throughout the device lifecycle

Hybrid learning scenario path selection and abstraction framework for smart verification of complex SoCs

Hybrid learning scenario path selection and abstraction framework for smart verification of complex SoCs

HUM-enhanced hybrid version of UVM with intelligent Fault injection and python based system predictors mechanisms

Embedded SoC System verification have become chief challenge in recent years due to increase in complex architectures and software’s. Even though SoC caters the needs for implementing the complex architectures, verification still remains crucial in terms of the accuracy, time computation and most importantly complex methodologies. Several methodologies were proposed, one such is Universal Verification Methodology (UVM), which occupies the major role in the SoC verification, UVM needs brighter light of research for the better improvisation in terms of the testing features and time of computation. Hence HUM (Hybrid Universal Methodology) was proposed with idea of extending the UVM by integrating the Fault Injection Systems along with Intelligent Predictors. The proposed tool has been tested with the IoTWireless Transceivers algorithms. The algorithms are targeted for the ARM architectures and results proved to be more vital.

Monitoring the state of materials in verification environment for IP architectures using python based verification mechanism

UVM is the most important mechanism in the field of SoC Verification. But complex characteristics, implementation difficulties in UVM still persist which leads to at most challenging part for the improvisation. To solve this issue, a new verification methodology called VEDA (Verification Environment for IP Architectures) which integrates python as the verification language is proposed. The powerful features of Python are used to bring the most versatile environment for verification and to make the UVM as the user friendly mechanism. The paper proposes the verification mechanism for the different IP’s which plays asignificant role in all IoT applications. Further the proposed method is being compared to existing UVM and also other existing python HDL tools and proved to be more advantages when compared to the existing methodologies.

Automated Bug Resistant Test Intent with Register Header Database for Optimized Verification

The biggest challenge in the verification industry is to create a sufficient number of valid test cases to acquire the desired coverage closure. The design complexity is relentlessly increasing with the number of gates, IPs, embedded processors, software content, and many more. It diverts the research once again to a point, where verification needs a productivity boost to cope with increasing design complexity. The extensive SoC design verification processes are using different execution platforms like simulation, emulation and FPGA prototyping. Each of these platforms requires different ways of specifying tests. The productivity and time demand a single test intent to reuse it across all verification execution platforms. Universal verification methodology (UVM) provides a verification efficiency jump from directed tests to constraint random tests. Synthesis allows the design productivity to jump from gate level to RTL level. Similarly, the SoC verification needs a higher-level of abstraction for automation enactment across all execution platforms. The proposed work derives a test intent on a UVM register abstraction testbench to generate automated test cases. It also assists in the improved functional coverage metric through bug resistant algorithm. The testbench also saves the manual effort of writing test cases. The work improves the simulation time, CPU time, and functional coverage closure in lesser number of transactions as compared to state of the art test benches.

STEPS OF VERIFICATION AND VALIDATION ROUTE AIMED AT OBTAINING THE SOC MODEL ABLE TO PERFORM TARGET TASKS AND ALGORITHMS WITH SPECIFIED CHARACTERISTICS

In order to ensure the convergence of SoC design based on its performance on real applications the entire route of SoC development starting with the architectural design to the qualification tests for topological netlist should be focused on the early localization of performance issues and the confirmation of consumer characteristics of SoC before its tapeout. The article describes some of the details of of SoC verification flow, based on the convergence of performance requirements. Also the results of the work of tools used in research of SoC and its components at various abstraction levels are presented. Verification flow is based on the usage of templated test environments and unified performance analysis tools. Method of description of input stimuluses based on graphs is proposed. This method allows recovering the scenarios which discovered errors and simulateing of real traffic. Steps of system verification and validation route, oriented to the SoC model capable to perform targeted objectives and algorithms with preset characteristics are proposed. An example of a system verified by principle of performance metrics control is given.

Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification

Modern system-on-chip (SoC) designs comprise programmable cores, application-specific accelerators, and I/O devices. Accelerators are controlled by software/firmware and functionality is implemented by this combination of programmable cores, firmware, and accelerators. Verification of such SoCs is challenging, especially for system-level properties maintained by a combination of firmware and hardware. Attempting to formally verify the full SoC design with both firmware and hardware is not scalable, while separate verification can miss bugs. A general technique for scalable system-level verification is to construct an abstraction of SoC hardware and verify firmware/software using it. There are two challenges in applying this technique in practice. Constructing the abstraction to capture required details and interactions is error-prone and time-consuming. The second is ensuring abstraction correctness so that properties proven with it are valid. This paper introduces a methodology for SoC design and verification based on the synthesis of instruction-level abstractions (ILAs). The ILA is an abstraction of SoC hardware which models updates to firmware-visible state at the granularity of instructions. For hardware accelerators, the ILA is analogous to the instruction-set architecture definition for programmable processors and enables scalable verification of firmware interacting with hardware accelerators. To alleviate the disadvantages of manual construction of abstractions, we introduce two algorithms for synthesis of ILAs from partial description called templates. We then show how the ILA can be verified to be correct. We evaluate the methodology using a small SoC design consisting of the 8051 microcontroller and two cryptographic accelerators. The methodology uncovered 15 bugs.

Разработка RN-моделей аналоговых СФ-блоков для верификации смешанных СнК

Разработка RN-моделей аналоговых СФ-блоков для верификации смешанных СнК

Verification and Test

This issue is focused on the special issue on “Emerging Challenges and Solutions in SoC Verification” from Guest Editors Magdy Abadir, Jayanta Bhadra, Wen Chen, and Li-C Wang. This special issue on verification is very timely, as new developments demand new verification techniques. For instance, the increasing heterogeneity of on-chip-systems (mainly to increase the power end energy efficiency; see also IEEE Design&Test issue on Dark Silicon, http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=7862860&punumber=6221038 ) makes verification more complex. Also, the newest trends in application, such as Internet-of-Things, require new verification approaches. The guest editors also present an article on “Challenges and Trends in Modern SoC Design Verification” to round up this interesting special issue. Many thanks to our guest editors for bringing the newest developments to IEEE Design&Test .

A High-Performance SoC Debug Platform

The vast increasing complexity of SoC design makes chip verification and debugging an extremely difficult task. In this paper we present a highly efficient run-stop-resume based SoC Debug Platform to deal with this problem. This platform allows one to observe any signals in the Intellectual Properties (IPs) of a SoC system during the normal system by implanting three powerful debug-trigger mechanisms into the SoC, namely cycle-based, event-based, and hardware-software cross-trigger-based mechanisms. With this platform, both hardware and software designers can work together on a common debugging environment from the very beginning so as to greatly increase debugging efficiency. Furthermore, we have also developed a design automation program called DASDEP ( D esign A utomation S ystem for SoC D E bug P latfrom) that can help users add design-for-debug circuitry into the SoC design and setup the required debug environment. DASDEP also provides a user-friendly interface for the whole debug process. This program together with the three debug mechanisms allows the SoC verification and debugging to be accomplished much more easily and efficiently than the conventional debug methods.

A 1.83 μJ/Classification, 8-Channel, Patient-Specific Epileptic Seizure Classification SoC Using a Non-Linear Support Vector Machine.

A non-linear support vector machine (NLSVM) seizure classification SoC with 8-channel EEG data acquisition and storage for epileptic patients is presented. The proposed SoC is the first work in literature that integrates a feature extraction (FE) engine, patient specific hardware-efficient NLSVM classification engine, 96 KB SRAM for EEG data storage and low-noise, high dynamic range readout circuits. To achieve on-chip integration of the NLSVM classification engine with minimum area and energy consumption, the FE engine utilizes time division multiplexing (TDM)-BPF architecture. The implemented log-linear Gaussian basis function (LL-GBF) NLSVM classifier exploits the linearization to achieve energy consumption of 0.39 μ J/operation and reduces the area by 28.2% compared to conventional GBF implementation. The readout circuits incorporate a chopper-stabilized DC servo loop to minimize the noise level elevation and achieve noise RTI of 0.81 μ Vrms for 0.5-100 Hz bandwidth with an NEF of 4.0. The 5 × 5 mm (2) SoC is implemented in a 0.18 μm 1P6M CMOS process consuming 1.83 μ J/classification for 8-channel operation. SoC verification has been done with the Children's Hospital Boston-MIT EEG database, as well as with a specific rapid eye-blink pattern detection test, which results in an average detection rate, average false alarm rate and latency of 95.1%, 0.94% (0.27 false alarms/hour) and 2 s, respectively.

A High-Performance SoC Debug Platform

The vast increasing complexity of SoC design makes chip verification and debugging an extremely difficult task. In this paper we present a highly efficient run-stop-resume based SoC Debug Platform to deal with this problem. This platform allows one to observe any signals in the Intellectual Properties (IPs) of a SoC system during the normal system by implanting three powerful debug-trigger mechanisms into the SoC, namely cycle-based, event-based, and hardware-software cross-trigger-based mechanisms. With this platform, both hardware and software designers can work together on a common debugging environment from the very beginning so as to greatly increase debugging efficiency. Furthermore, we have also developed a design automation program called DASDEP (Design Automation System for SoC DEbug Platfrom) that can help users add design-for-debug circuitry into the SoC design and setup the required debug environment. DASDEP also provides a user-friendly interface for the whole debug process. This program together with the three debug mechanisms allows the SoC verification and debugging to be accomplished much more easily and efficiently than the conventional debug methods.

SoC Verification Platforms Using HW Emulation and Co-modeling Testbench Technologies

SoC Verification Platforms Using HW Emulation and Co-modeling Testbench Technologies

Challenges and Novel Solutions for SoC Verification

Hundred million gates SoC designs are all over the place with the trend of doubling the scale in up-coming years. Meanwhile time-to-market makes the situation even more difficult. More and more effort has been allocated onto SoC verification in order to tackle the challenges, including the improvement of software-based verification performance, formal verification, hardware acceleration as well as unified verification. But innovation is still needed, as the existing solution won’t be able to handle efficiently of the increasing design size. This paper will first try to address all major issues which would challenge the SoC verification execution as well as quality. At the second part of this paper, we will discuss how Cadence addresses these challenges including, but not limited to, early software development, metric driven verification, formal verification application, Hardware/Software integrated validation and low power. Through close partnership with major industry leaders, Cadence’s solution has been proven to provide a substantial turn-around time reduction while maintaining high quality of result for various SoC projects.

SystemC fine-grained HW–SW fully heterogeneous WSN simulation and UML metamodel behavioural extraction

Wireless sensor networks are becoming an essential part of our lives, being frequently used for monitoring and control applications. It is essential that these networks be modelled before their deployment so as to identify the possible problems that may arise. SystemC is fast becoming an important modelling paradigm in the context of SoC design and verification, as well as other fields that require accurate (sometimes Transaction Level Modelled) characterization of digital processes (i.e.: communication on a bus interface, over a radio channel, etc). SystemC has successfully been used in the IDEA1 WSN exploration framework to model wireless sensor networks at the timed functional level of abstraction. As a first contribution, we refined the initial implementation of IDEA1 to cope with a finer-grade simulation of the node hardware, going beyond the timed functional description of the node and enabling support for a bus cycle-accurate simulation. The new and improved version is called IDEA1TLM and can also model the software aspect of the nodes in question by means of a custom-built instruction set simulator called BLISS. The second part of this contribution focuses on extracting the metamodel from SystemC source files. The metamodel is the information which can be generated concerning the model; in our case, a diagram representation with states and transitions between them. Because current work focuses on generating C++ code (SystemC-compliant) from UML metamodels, there is no support to achieve this in reverse. We developed a tool called DiaSig that takes SystemC source files as input and generates UML diagrams of the model in SVG format.

SOC HW/SW co‐verification based debugging technique

PurposeIncreasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. SOC HW/SW co‐verification technique seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. The purpose of this paper is to study a run‐time RTL debugging methodology for a FPGA‐based co‐verification system.Design/methodology/approachThe debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI‐extended bus, instead of inserting extra scan‐chain logic, so the overhead for area is reduced.FindingsThis method provides internal nodes probing on an event‐driven co‐verification platform and achieves full observability for DUT. The experiment shows that, compared with a similar method, the area overhead for debug logic is reduced by 30‐50 per cent and compile time is shortened by 40‐70 per cent.Originality/valueThe proposed debugging technique achieves 100 per cent observability and can be applied to both RTL and gate‐level verification. The debugging tool is embedded into HDL simulator using Verilog VPI callback, so DUT signals are displayed together with testbench signals in the same waveform viewer. New value of DUT signal is read from FPGA whenever it changes, which allows run‐time debug.

Vector mode based hardware acceleration and emulation for LDPC application

PurposeWith the rapid development of integrated circuits, verification of SOC chips has become a great challenge due to its integration and complexity. Traditional software‐based simulation methodology cannot meet verification needs. Therefore, FPGA‐based hardware acceleration technologies are requested in SOC verification. The classic methodology of hardware acceleration downloads the DUT (Device under Test) to the FPGA, while part of RTL codes and test bench is still run on the simulator in the workstation. Research found that the speed bottleneck of this methodology is mostly caused by the ping‐pong mode of data transmission between workstation software and the FPGA emulator, thus resulting in that channel transmission time takes too much proportion of total time. The purpose of this paper is to present a vector mode based hardware/software co‐emulation methodology, which leverages a pipeline structure to transmit, receive and buffer data. This methodology reduces the communication overhead by carrying out a parallel mechanism in that while user's design is under test in the emulator, signal data are transmitting in the channel simultaneously, thus increasing the speed of hardware acceleration and emulation.Design/methodology/approachThe methodology of hardware acceleration proposed by this paper intercepts data for once from the emulation process of a traditional platform as test bench and utilizes direct memory access (DMA) channel to speed up data transfer, as well as increasing reasonable data caching mechanism, which reduces the ratio of channel transmission time in the entire emulation time, achieving accelerating emulation.FindingsThe proposed methodology and traditional hardware acceleration approach were tested on a quasi‐cyclic low‐density parity‐check (LDPC) decoder. Experiment results indicate that the proposed method can increase communication throughput 140 times compared with the traditional approach.Originality/valueA vector mode based hardware/software co‐emulation methodology is presented in the paper. Higher communication throughput can be achieved by carrying out a parallel mechanism, as well as leveraging a pipeline structure to transmit, receive and buffer data.

A System-Level SOC Verification Method based on Hardware Accelerator

A system-level SOC verification method based on hardware accelerator is proposed in this paper. The storage mapping relationship is designed according to storage characteristics of the hardware accelerator, and the whole testbench is put into the accelerator directly, resulting in a quick migration to accelerator and an optimized memory area. In order to ensure the comprehensiveness, complexity and authenticity, the system feature description is extracted from different application scenarios, and the test cases are derived from the paths of data flow and control flow. Additionally, the system debugging is simplified by controlling the acceleration processing with the method of trigger-driver-based state transition diagram. By adopting the system-level verification method proposed in this paper, RTL design of a DSP chip is verified and the experiment results demonstrate an immense acceleration effect and a high accuracy in bug locating. Finally the DSP chip is implemented in 0.18um CMOS process and it works properly. 