Monitoring the state of materials in verification environment for IP architectures using python based verification mechanism

Abstract

UVM is the most important mechanism in the field of SoC Verification. But complex characteristics, implementation difficulties in UVM still persist which leads to at most challenging part for the improvisation. To solve this issue, a new verification methodology called VEDA (Verification Environment for IP Architectures) which integrates python as the verification language is proposed. The powerful features of Python are used to bring the most versatile environment for verification and to make the UVM as the user friendly mechanism. The paper proposes the verification mechanism for the different IP’s which plays asignificant role in all IoT applications. Further the proposed method is being compared to existing UVM and also other existing python HDL tools and proved to be more advantages when compared to the existing methodologies.