Beyond UVM for practical SoC verification

Abstract

As the size and complexity of SoC design grow, an efficient and structured verification environment is becoming more important than ever before. It is because many engineers with different knowledge and skills are involved in SoC verification, and they have to deal with different aspects of verification. This paper looks over the diversity of SoC verification and suggests a practical application method of UVM (Universal Verification Methodology) to build an efficient and structured verification environment which meets various requirements of SoC verification. This paper shows standardized and well-organized testbench architecture that includes directory structure of testbench files, and mechanism such as interface and handles across the components. The proposed UVM application method helps testbench developers maintain consistency of testbenches and reduce the quality gap among verification works that are done by multiple verification engineers, by using standardized testbench. It ensures that IP verification engineers do their job independently and the testbenches can be reused in top level verification environment. In addition, it provides a good infrastructure to hardware designers, who have little knowledge about verification languages and methodologies, and who want to write directed test cases only. The proposed method has been validated with a set of reference testbenches developed for an application processor SoC.