Challenges and Novel Solutions for SoC Verification

Abstract

Hundred million gates SoC designs are all over the place with the trend of doubling the scale in up-coming years. Meanwhile time-to-market makes the situation even more difficult. More and more effort has been allocated onto SoC verification in order to tackle the challenges, including the improvement of software-based verification performance, formal verification, hardware acceleration as well as unified verification. But innovation is still needed, as the existing solution won’t be able to handle efficiently of the increasing design size. This paper will first try to address all major issues which would challenge the SoC verification execution as well as quality. At the second part of this paper, we will discuss how Cadence addresses these challenges including, but not limited to, early software development, metric driven verification, formal verification application, Hardware/Software integrated validation and low power. Through close partnership with major industry leaders, Cadence’s solution has been proven to provide a substantial turn-around time reduction while maintaining high quality of result for various SoC projects.