Automated Bug Resistant Test Intent with Register Header Database for Optimized Verification

Abstract

The biggest challenge in the verification industry is to create a sufficient number of valid test cases to acquire the desired coverage closure. The design complexity is relentlessly increasing with the number of gates, IPs, embedded processors, software content, and many more. It diverts the research once again to a point, where verification needs a productivity boost to cope with increasing design complexity. The extensive SoC design verification processes are using different execution platforms like simulation, emulation and FPGA prototyping. Each of these platforms requires different ways of specifying tests. The productivity and time demand a single test intent to reuse it across all verification execution platforms. Universal verification methodology (UVM) provides a verification efficiency jump from directed tests to constraint random tests. Synthesis allows the design productivity to jump from gate level to RTL level. Similarly, the SoC verification needs a higher-level of abstraction for automation enactment across all execution platforms. The proposed work derives a test intent on a UVM register abstraction testbench to generate automated test cases. It also assists in the improved functional coverage metric through bug resistant algorithm. The testbench also saves the manual effort of writing test cases. The work improves the simulation time, CPU time, and functional coverage closure in lesser number of transactions as compared to state of the art test benches.