Velocity Saturation Region Research Articles

A non-GCA model for ground-plane MOSFETs

A non-GCA (Gradual Channel Approximation) model continuous into the velocity saturation region is developed for ground-plane bulk MOSFETs. The Ids-Vds characteristics generated by both the n = 1 and the n = 2 models are consistent with 2-D simulations. By incorporating source and drain series resistance into the model, it is shown that the model can reproduce the Ids-Vds data of 20 nm bulk MOSFETs published in the literature.

A Non-GCA DG MOSFET Model Continuous into the Velocity Saturation Region

Continuous models are developed that go beyond the gradual channel approximation and extend MOSFET ${I}$ – ${V}$ characteristics into the velocity saturation region with finite output conductance. Both the ${n} = {1}$ and ${n} = {2}$ models have been employed. It is shown that the standard relation of channel length modulation for constant mobility must be modified for velocity saturation because the drain current is not simply inversely proportional to the channel length. Regional approximations are applied to derive the explicit expressions for the output conductance in the velocity saturation region in terms of basic device parameters.

The Effect of Base–Emitter Interfacial Layer on the Organic Permeable Base Transistor’s Characteristics

ABSTRACTA thin interfacial layer of 20 nm has been introduced to increase the barrier from 0.9 to 1.1 eV or 1.2 eV or 1.4 eV between the base and emitter of an organic permeable base transistor (OPBT). The effect of this barrier height has been studied through the OPBTs fabricated with 5,5′′′′′-dihexyl-2,2′:5′,2′′:5′′,2′′′:5′′′,2′′′′:5′′′′,2′′′′′-sexithiophene as an active material for forming emitter and collector regions. First time, it has been observed that output characteristics of OPBT’s mimics the near-ideal characteristics of the metal oxide semiconductor field effect transistor and experiences significant change as the barrier height increases and the device enters into the velocity saturation region at lower applied voltage. The gain factor (β) has been found to vary from 0.5 to 2.7 µAV–2 with the increase in the barrier from 0.9 to 1.2 eV while at the high barrier of 1.4 eV, it is almost negligible.

Analysis of the impedance field of saturated MOSFETs and drain thermal noise

The effect of the velocity saturation region (VSR) on the impedance field of proto-type MOSFET devices, which operate in the saturation region, was investigated to analyze the drain thermal noise. An enhanced impedance field for the drain thermal noise was derived based on the well-known physical analyses of MOSFET noise. The mechanism of the VSR in inducing the drain thermal noise has been explicated by using a self-consistent equivalent circuit model of the saturated MOSFETs. This alternative description was found to be consistent with the analytical derivation. The present analysis has been demonstrated to be consistent with the behavior of empirical drain thermal noise.

An Analytic Model for Estimating the Length of the Velocity Saturated Region in Double Gate Bilayer Graphene Transistors

An analytical model for surface potential of asymmetric double gate Bilayer Graphene (BLG) transistors is presented on the basis of two‐dimensional Poisson’s equation. To verify the accuracy of potential model, the modelling data are compared with the simulation data of FlexPDE program and a good agreement is observed. From surface potential expression, the device behaviour in velocity saturation region is investigated. As a result, lateral electric field and length of velocity saturation region (Ld) are formulated and their dependence on several device parameters is carefully examined.

Drain current model for strained-Si/Si1−xGex/strained-Si double-gate MOSFETs including quantum effects

In this paper, we present an accurate semi-analytical model for the I−V characteristics of nanoscale double-gate (DG) strained nMOSFETs. The structure makes use of two strained-silicon (S-Si) channels for current flow on both sides of a middle Si1−xGex layer. Taking carrier confinement effect into account, we have developed an efficient yet exact model for the inversion charge sheet density in the channel. The model is utilized for predicting the threshold voltage. In addition, it is used to find the drain current of the device for all regions of operation. Additionally, the channel length modulation in the device has been investigated and a model for the length of velocity saturation region is introduced, which enables the model to be applied to short channel devices. To assess the accuracy of the proposed model, the results of the model are compared to those of the numerical simulations and found to be accurately predicting the simulation results.

A New Impact-Ionization Current Model Applicable to Both Bulk and SOI MOSFETs by Considering Self-Lattice-Heating

In existing impact-ionization current (J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> ) models for short-channel MOSFETs, various models for the characteristic ionization length (I) or the velocity-saturation region length (l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) have been developed by using the polynomial-fitting method in order to model the bias dependence of the maximum electric field (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) in the channel. This paper proposes a bias-voltage- and gate-length-dependent effective maximum electric field (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m,eff</sub> ) based on energy-balance equation, aimed at obtaining an accurate expression of E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> to increase the accuracy of the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> model for deep submicrometer devices. This new method overcomes the complicated modeling of I, avoids the extraction of different fitting constants for different devices, and enables unique extraction of the impact-ionization coefficients (A and B) for different devices. This improved model demonstrates excellent agreements with the numerical data of nMOSFETs from a 90-nm-technology wafer file. Only one unique set of parameters is needed to fit the data from devices with different biases and lengths for the same technology node. Moreover, since the lattice temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">l</sub> ) is built in the formulation of E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m,eff</sub> , a compact I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> model with self-lattice-heating is developed, which also accounts for the excess substrate current observed in the SOI devices due to carrier heating in the channel.

An Analytical Compact Direct-Current and Capacitance Model for AlGaN/GaN High Electron Mobility Transistors

ABSTRACTWe develop an analytical model for the Direct-Current (DC) and capacitance-voltage (CV) characteristics of AlGaN/GaN High Electron Mobility Transistors (HEMTs), providing accurate predictions of the transconductance and the gate capacitance in both linear and velocity saturation regions. The models provide an accurate and smooth connection in the area near the knee point for the DC characteristics, which is attributed to precise descriptions of the channel charge. An accurate model for the low-field mobility of the two dimensional electron gases (2DEG) has been developed, considering the nonmonotonic dependence of the carrier velocity on the electric field perpendicular to the channel for the first time. The calculated transconductance and output conductance are proved accurate and to have high order continuity, especially in large voltage biases, which is hard for some other analytical or numeral models. The gate capacitance has been obtained analytically and verified by experimental data. The slight decrease in the measured gate-to-source capacitance over the velocity saturation region which indicates the results of neutralization of donors and the contribution of the free electron in the AlGaN layer has been modeled accurately and smoothly for the first time. The predicted cut-off frequency is in excellent agreements with measured data over the full range of applied biases. The models are implemented into the HSPICE simulator for the DC, AC and transient simulations, with good speed and convergence characteristics.

2-D Analytical Model for Current–Voltage Characteristics and Transconductance of AlGaN/GaN MODFETs

A threshold-voltage-based 2-D analytical model for the current-voltage characteristics of the AlGaN/GaN modulation-doped field-effect transistors (MODFETs) is presented. In this paper, the conventional charge-control model is improved by employing the Robin boundary condition when solving the 1-D Schrodinger equation in the low longitudinal-field region and introducing an adjustable eigenvalue during the solution of the 2-D Poisson's equation in the velocity-saturation region. A modified Polyakov-Schwierz mobility model, as well s a low-field mobility model, has been developed. In addition, the nonlinear polarization effects at the AlGaN/GaN interface and the parasitic source/drain resistances are incorporated. Our model predicts the drain current of a second-order continuity, and both the transconductance and output conductance can be determined analytically. We validate the model with experimental data for and MODFETs, respectively, and obtained good agreements.

Quasi 3-D Velocity Saturation Model for Multiple-Gate MOSFETs

This paper presents a quasi-3D velocity saturation model for a multiple-gate MOSFET based on a calculation of Gauss's equation. A new and compact velocity saturation region length is derived from a simple approximation of the electric field distribution in the pinchoff region. It is found that the length of the velocity saturation region increases with the increment of gate length and fin width. This new model is used to derive an analytical expression of a substrate current for a trigate MOSFET. In order to improve the accuracy of the substrate current model, the newly derived substrate current model introduces a parasitic potential drop across a thin-extension region and a dimensionless fitting parameter. A body-tied trigate MOSFET is fabricated on a bulk wafer so that the substrate current could be measured by its body contact. The new substrate current model is then compared with measurement data for a trigate MOSFET, and good agreement is observed

Modelling velocity saturation and kink effects in p-channel polysilicon thin-film transistors

Experimental measurements and full-2D numerical simulations show that velocity saturation effects in polysilicon thin-film transistor (TFTs) cannot be neglected in order to obtain a precise modelling of output characteristics. Since full-2D numerical simulations are time consuming and unpractical for circuit simulations, we have developed a new quasi-2D model, that takes into account both velocity saturation effects and the presence of a longitudinal electric field in the Poisson's equation, and includes the effect of parasitic bipolar transistor (PBT) action to reproduce kink effect. The agreement of the quasi-2D model with experimental data from p-channel polysilicon TFTs is very satisfactory even for short channel device, and the presence of a velocity-saturated region with a nearly constant free carrier concentration is reproduced without introducing further assumptions.

A New Method to Extract Carrier Velocity in Sub-0.1-$mu$m MOSFETs Using RF Measurements

A novel RF method based on the accurate extraction of the gate–source channel capacitance and intrinsic transconductance from measured $S$ -parameters is proposed to determine the effective carrier velocity of sub-0.1- $mu$ m MOSFETs in the velocity saturation region. This method is developed to avoid the errors associated with underestimated charge in traditional ones. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed along with the linear dependence of measured electron velocity on $1/L_ poly$ in bulk N-MOSFETs with a channel length of less than 0.085 $mu$ m. This extracted result is more accurate than that of previous methods, because $v_ eff$ is directly determined from the gate–source channel capacitance at high V $ ds$ instead of that at V $ ds=0$ .

Do hot electrons cause excess noise?

The open question whether excess noise is due to hot electrons or not is addressed for the first time by solving the full Langevin Boltzmann equation. Not only the bulk case is analyzed but also devices. In contrast to the well-known Monte Carlo method this new approach allows the investigation of the spatial origin of the terminal current noise. It is shown, that excess noise in devices is mainly due to cold or warm electrons. The contribution of hot electrons in a velocity saturation region is found to be negligible. This corroborates previous findings based on the less accurate impedance field method.

An improved substrate current model for ultra-thin gate oxide MOSFETs

In existing substrate current I sub models for short channel MOSFETs, the new model of the characteristic ionization length l or the velocity saturation region length L d has been developed by using the polynomial fitting method in order to represent the variation of maximum electric field E m with bias voltages in channel. This work proposes a bias-voltage- and gate-length-dependent parameter η which was previously treated as a process-dependent constant, aimed at obtaining an accurate expression of E m to increase the accuracy of I sub model for ultra-deep submicron devices with ultra-thin gate oxides. This new method overcomes the complicated modeling of characteristic ionization length l, and avoids the extractions of different fitting constant η corresponding to different devices. It also warrants the unique extraction of impact ionization coefficients A i and B i. Compared with some existing I sub models, the improved one presents more excellent agreements with the experiments of ultra-thin gate oxide ( t ox = 1.24 nm) LDD NMOSFETs on 90 nm CMOS technology, especially in the high electric field region. Meanwhile, the new I sub model accurately simulates the shift of the peak of substrate current along the gate bias axis with the shortening of gate length which usually occurs in ultra-thin gate oxide devices, helpful to the lifetime prediction of sub-100 nm devices.

Channel noise modeling of deep submicron MOSFETs

This brief presents a new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs. Based on the new channel noise model, the simulated noise spectral densities of the devices fabricated in a 0.18 /spl mu/m CMOS process as a function of channel length and bias condition are compared to the channel noise directly extracted from RF noise measurements. In addition, the hot electron effect and the noise contributed from the velocity saturation region are discussed.

Models for subthreshold and above-threshold currents in 0.1-μm pocket n-MOSFETs for low-voltage applications

We present a model for subthreshold current in deep-submicrometer pocket n-MOSFETs based on the diffusion current transport equation, the quasi-two-dimensional (2-D) Poisson equation and a doping-density-dependent mobility model, and a model for above-threshold current in deep-submicrometer pocket n-MOSFETs based on the drift-diffusion current transport equation for nonuniformly doped MOSFETs, the charge-sheet approximation, a solution of the one-dimensional (1-D) Poisson equation, a quasi-2-D model for the velocity saturation region, longitudinal- and transverse-field-dependent mobility models. The analytic models for subthreshold and above-threshold currents are used to efficiently construct viable design spaces locating well-designed 0.1-/spl mu/m pocket n-MOSFETs that meet all the device design specifications of off-state (leakage) current, on-state (drive) current, and power-supply voltage. The model for subthreshold current correctly predicts an increase in off-state current in sub-100 nm pocket n-MOSFETs. The model for above-threshold current generates I/sub D/-V/sub DS/ characteristics of a variety of deep-submicrometer pocket n-MOSFETs.

Modeling of thermal noise in short-channel MOSFETs at saturation

An analytical formula of excessive thermal noise in short-channel MOSFETs at saturation is developed following the approach used for GaAs JFET or MESFET by Statz, Haus, and Pucel. It is taken into account that the noise generated in the velocity saturation region comes from randomly generated dipole layers which propagate toward the drain contact without relaxation. Simulation of the derived formula shows that the velocity saturation region plays a crucial role in determining excessive thermal noise in short-channel MOSFETs. The proposed thermal noise formula is confirmed by the comparison to the published experimental results of high-frequency noise in the short-channel nMOSFET of channel length 0.7 μm at saturation.

An analytic model for estimating the length of the velocity saturated region in GaAs MESFETs

An analytical model is presented for estimating the length of the portion of an FET channel with velocity saturated carriers. The model is based on previous work proposed by Pucel et al. [1974, 1975], and has been adapted to remove discontinuities between extreme bias conditions. The need for complicated numerical solutions has also been removed making the model suitable for use with circuit simulators. Results obtained from the model agree well with previously proposed models over a wide range of bias conditions where velocity saturation can be either dominant or negligible, depending on the overall channel length and bias conditions.

Dependence of the domain-wall velocity on the driving field in garnet films

The dependence of the domain-wall velocity on the amplitude of the driving magnetic field pulses is investigated in an iron garnet film of the (YSmCa)3(FeGe)5O12 system with a (111) orientation. The results obtained are analyzed from the standpoint of existing theory. A maximum corresponding to the disruption of steady-state motion is observed on the dependence. Thereafter, the velocity at first decreases sharply and then increases. It is theorized that a process involving the periodic generation, propagation, and annihilation of horizontal Bloch lines occurs in the wall in this period. Data are obtained for the velocity saturation region, which confirm a previously proposed empirical formula and a theoretical model, according to which the saturation regime corresponds to a state of chaos.

Approximation of the length of velocity saturation region in MOSFET's

This work presents an accurate approximation of the length of velocity saturation region (LVSR) based on the calculation of one-dimensional (1-D) electric field distribution near the drain region of MOSFET's. Results show that for short-channel devices (<1 /spl mu/m), the LVSR values calculated with the new model are much smaller than the conventional approach. The new model agrees well with the MINIMOS simulation results. According to the simulation and theoretical results, the length of velocity saturation region increases gradually with the drain bias and channel length.