Abstract
An analytical model is presented for estimating the length of the portion of an FET channel with velocity saturated carriers. The model is based on previous work proposed by Pucel et al. [1974, 1975], and has been adapted to remove discontinuities between extreme bias conditions. The need for complicated numerical solutions has also been removed making the model suitable for use with circuit simulators. Results obtained from the model agree well with previously proposed models over a wide range of bias conditions where velocity saturation can be either dominant or negligible, depending on the overall channel length and bias conditions.
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