VCO-based Analog-to-digital Converter Research Articles

A Reconfigurable, Nonlinear, Low-Power, VCO-Based ADC for Neural Recording Applications.

Neural recording systems play a crucial role in comprehending the intricacies of the brain and advancing treatments for neurological disorders. Within these systems, the analog-to-digital converter (ADC) serves as a fundamental component, converting the electrical signals from the brain into digital data that can be further processed and analyzed by computing units. This research introduces a novel nonlinear ADC designed specifically for spike sorting in biomedical applications. Employing MOSFET varactors and voltage-controlled oscillators (VCOs), this ADC exploits the nonlinear capacitance properties of MOSFET varactors, achieving a parabolic quantization function that digitizes the noise with low resolution and the spikes with high resolution, effectively suppressing the background noise present in biomedical signals. This research aims to develop a reconfigurable, nonlinear voltage-controlled oscillator (VCO)-based ADC, specifically designed for implantable neural recording systems used in neuroprosthetics and brain-machine interfaces. The proposed design enhances the signal-to-noise ratio and reduces power consumption, making it more efficient for real-time neural data processing. By improving the performance and energy efficiency of these devices, the research contributes to the development of more reliable medical technologies for monitoring and treating neurological disorders. The quantization step of the ADC spans from 44.8 mV in the low-amplitude range to 1.4 mV in the high-amplitude range. The circuit was designed and simulated utilizing a 180 nm CMOS process; however, no physical prototype has been fabricated at this stage. Post-layout simulations confirm the expected performance. Occupying a silicon area is 0.09 mm2. Operating at a sampling frequency of 16 kS/s and a supply voltage of 1 volt, this ADC consumes 62.4 µW.

Voltage-controlled oscillator based analog-to-digital converter in 130-nm CMOS for biomedical applications

Medical implants and portable wireless sensors are the most serious of biomedical applications due to the dependence on limited battery lifetime. Consequently, energy efficiency integrated circuits designs must be put to higher attention. A particular distinguishing contribution of this paper is its focus on the power consumption that affects battery life and the heat dissipated for biomedical applications. This paper demonstrates a power-efficient implementation of analog-to-digital converter (ADC) based on voltage-controlled oscillator (VCO) to convert the collected analog vital signs into digital data for digital signal processing. The current-starved scheme is employed to implement the VCO efficiently with five-stage which leads to high savings in power and area. D-flip flop (D-FF) scheme is proposed to simplify the hardware architecture of the proposed reset counter. The proposed architecture is implemented with 130 nm CMOS technology and it can perform conversion of analog input signal to digital output using a straightforward hardware structure. The proposed VCO-based ADC achieves improvement in energy saving. Simulation results confirm that this work attains a power dissipation of 0.257 mW and active area of 0.007 mm2, and a very good Walden FOMW of 125 dB. The proposed methodology can implement any number of bits of the ADC by using the appropriate voltage-controlled oscillator with the convenient reset counter.

A fully-digital calibration algorithm for VCO-based ADC

In this paper, an all-digital foreground calibration algorithm is proposed to mitigate harmonic distortions in open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converters (ADCs). By calculating the 3rd-order nonlinearity coefficients of the VCO-based ADC digital output, a look-up table is established to achieve nonlinearity calibration. A 40 MHz-bandwidth VCO-based ADC with 5 bit quantization and a clock frequency of 1.6 GHz was designed and simulated in 40 nm CMOS GP process, while the proposed calibration algorithm is implemented in a FPGA board. The experimental results show that the ADC signal-to-noise-distortion ratio (SNDR) is improved from 40.8 dB to 56.4 dB, and the ADC signal-to-noise ratio (SNR) is 58.9 dB, with limited hardware resources and only 104 clock cycles to converge.

A Pseudo-Virtual Ground Feedforwarding Technique Enabling Linearization and Higher Order Noise Shaping in VCO-Based ΔΣ Modulators

This article presents a third-order voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) that leverages pseudo-virtual ground (PVG) feedforwarding (FF), linearizing the VCOs and enabling higher order noise shaping with a single feedback digital-to-analog converter. This technique leads to a power-efficient ADC implementation with a wide dynamic range. The ADC is fabricated in a 65-nm process and achieves a 92.1-dB SNDR in a 2.5-kHz bandwidth. This results in a state-of-the-art 179.6-dB figure-of-merit (FoM) among previously published VCO-based ADCs. The PVG FF technique allows the ADC to attain extremely high linearity, 123-dB peak SFDR, with a wide 1.8-Vpp differential input range. The ADC maintains performance with up to 200-mV variation on the 0.8-V supply and across temperatures from 0 to 70 °C.

Measurement of electromagnetic field immunity of voltage-controlled oscillator-based analog-to-digital converters in 28 nm CMOS technology

Internet-of-Things (IoT) devices are compact and low power. A voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) benefits from scaled CMOS transistors in representing analog signals in the time domain and therefore meets those demands. However, we find the potential drawback of VCO-based ADCs for the electromagnetic susceptibility (EMS) to RF disturbances that are essentially present in an IoT environment. It is exhibited that the single and even differential designs of VCO-based ADC suffer from the EMS by RF disturbance, which behaves differently from the known common-mode noise rejection. A 28 nm CMOS 11-bit VCO-ADC prototype exhibits sensitivity against RF signals in the widely used 2.4 GHz frequency band.

Linearity Enhancement of VCO-Based Continuous-Time Delta-Sigma ADCs Using Digital Feedback Residue Quantization

A linearity enhancement scheme for voltage-controlled oscillator (VCO)-based continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADCs) is proposed. Unlike conventional input feedforwarding techniques, the proposed feedforwarding scheme using digital feedback residue quantization (DFRQ) can avoid the analog summing amplifier, allow intrinsic anti-aliasing filtering (AAF) characteristic, and cause no switching noise injection into the input. A VCO-based CT ΔΣ ADC adapting the proposed DFRQ enables residue-only processing in the quantizer, avoiding the degradation of signal-to-noise and distortion ratio (SNDR) due to VCO nonlinearity. The use of DFRQ also reduces the voltage swing of integrators without the drawbacks caused by conventional input feedforwarding techniques. The performance evaluation results indicate that the proposed VCO-based CT ΔΣ ADC with DFRQ provides 30.3-dB SNDR improvement, reaching up to 83.5-dB in 2-MHz signal bandwidth.

Linearization of Voltage-Controlled Oscillators Using Floating-Gate Transistors

This brief presents a linearization method for the voltage-to-current (V-to-I) stage of voltage-controlled oscillators (VCOs). A floating-gate transistor is utilized at the VCO's input stage as a low-overhead method for V-to-I linearization. The resulting VCO is a ring oscillator with an extended linear voltage-to-frequency range. The ring oscillator VCO (RO-VCO) has also been included in a VCO-based analog-to-digital converter (VCO-ADC) to showcase how the linearization technique can be leveraged to improve system performance. The measured results from the linearized RO-VCO are compared to current state-of-the-art designs, and the VCO-ADC is compared to a standard architecture. The circuits were fabricated in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) process.

Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC

This paper presents a synthesizable lead-lag quantization technique for all-digital delta sigma (ΔΣ) analog-to-digital converters (ADCs) based on voltage-controlled oscillator (VCO). Synthesizable circuitry is proposed to realize this technique, including a lead-lag phase detector (LLPD) and a tri-level resistor digital-to-analog converter (TRDAC) for feedback. It distinguishes the leading and lagging phases in an N-stage dual-VCO quantizer so that the resolution increases from log2(N+1) bits to log2(2 ​N ​+ ​1) bits. The TRDAC is also used as biasing DAC and suppresses the process variation. Taking the digital-like analog/mixed-signal design flow, the proposed ADC is implemented in 28-nm CMOS technology occupying only 0.0039 ​mm2. The simulation results show that it consumes 0.552 ​mW ​at a 0.9-V power supply, and achieves a 66.9-dB signal-to-noise-and-distortion ratio (SNDR) at 900 ​MS/s over 6-MHz bandwidth. With a similar SNDR to prior works, this technique lowers the Figure-of-Merit (FoM) to 25.5 fJ/conv.-step.

A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows

This paper proposes a technique that uses the number of oscillation cycles (NOC) of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The analysis of the number of bit cycles, power and static performance shows that three adaptive bypass windows reduce power consumption, and decrease DNL and have similar INL, compared with the SAR ADC without bypass windows. In addition, a 1-bit split-and-recombination redundancy technique and a general bypass logic digital error correction method are proposed to address the settling issues and optimize the size of the bypass window. This design is implemented in 40 nm CMOS technology. The conversion frequency of the ADC reaches up to 30 MS/s. The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input, consuming 380 μW, down from 427 μW without multiple adaptive bypass windows, at a 1.1 V supply, resulting in a figure of merit (FoM) of 5.69 fJ/conversion-step.

A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones.

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta () analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 A at 1.8 V and the effective area is 0.12 mm. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.

A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator

A successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator is presented in this paper. The relationship between the input voltage and the number of oscillation cycles (NOC) to reach a VCO-comparator decision is explored, implying an inherent coarse quantization in parallel with the normal comparison. The NOC as a design parameter is introduced and analyzed with noise, metastability, and tradeoff considerations. The NOC is exploited to bypass a certain number of SAR cycles for higher power efficiency of VCO-based SAR ADCs. To cope with the process, voltage, and temperature (PVT) variations, an adaptive bypassing technique is proposed, tracking and correcting window sizes in the background. Fabricated in a 40-nm CMOS process, the ADC achieves a peak effective number of bits of 9.71 b at 10 MS/s. Walden figure of merit (FoM) of 2.4–6.85 fJ/conv.-step is obtained over a wide range of supply voltages and sampling rates. Measurement has been carried out under typical, fast-fast, and slow-slow process corners and 0 °C–100 °C temperature range, showing that the proposed ADC is robust over PVT variations without any off-chip calibration or tuning.

A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing

This paper introduces a voltage-controlled oscillator (VCO)-based nonuniform sampling (NUS) analog-to-digital converter (ADC), which shifts the conventional voltage-domain level crossing to the phase domain, thus eliminating the need for any continuous-time (CT) comparator or reference generator. It increases the signal bandwidth and reduces the implementation costs of both analog and digital circuitries compared to the existing voltage-domain NUS ADCs. The signal-to-quantization-noise ratio (SQNR) is improved by the first-order noise shaping and inherent dithering via the free-running oscillation of VCO. The quantization error of the proposed architecture is analyzed, and a phase-domain calibration on the VCO nonlinearity is proposed. Due to the mostly digital architecture and time-based nature of the proposed architecture, the performance and figure of merit (FOM) are expected to improve with the scaled technology. This prototype achieves 200-MHz bandwidth with 60-dB dynamic range (DR) and consumes 19.7 mW of power with an active area of 0.13 mm2 in 65-nm complementary metal–oxide–semiconductor (CMOS), where the nonuniform digital signal processing (DSP) is performed off chip. The estimated power and area of the nonuniform DSP including the calibration and decimation filter are 30 mW and 0.114 mm2, respectively.

A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration

This article presents a 14-bit 4-MS/s voltage-controlled oscillator (VCO)-based successive approximation register (SAR) analog-to-digital converter (ADC), where the metastability of the VCO-based comparator is exploited for the background calibration of mismatch errors. A closed-form behavioral analysis of VCO-based comparators has been studied in the presence of noise, showing that the metastability is of unique characteristics as compared to voltage-domain comparators, and the metastability can be evaluated quantitatively by observing the number of oscillation cycles. Deep metastability (DM) indicates a condition where the signal and noise are sufficiently small as compared to mismatch errors, based on which an analog background calibration technique is proposed. A decision stabilizer is employed to deal with the limit-cycle oscillations (LCOs). Fabricated in a 40-nm CMOS technology, the ADC prototype exhibits peak signal-to-noise-and-distortion ratio (SNDR) of 78.7 dB and >93-dB spurious-free dynamic range (SFDR) across nine samples. At 2 and 4 MS/s, the ADC, including calibration logic, consumes only 94 and $157~\mu \text{W}$ from a 1.1-V supply, achieving a peak Schreier figure of merit (FoM) of and 177.7 dB, respectively.

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m CMOS

This brief presents a 10-bit 5 MS/s hybrid analog-to-digital converter (ADC) combining successive approximation register (SAR) with voltage-controlled oscillator (VCO) in 0.18- $\mu \text{m}$ CMOS. Non-ideal factors from practical circuit implementations are theoretically considered and modeled in Simulink. To improve the linearity and the reliability of the bootstrapped switch circuit, the body-effect compensation is adopted. The asynchronous clock generation circuit with a variable-time control cell is presented, which optimizes the DAC settling time of the MSB DAC and LSB DAC in an SAR conversion. Verilog codes and a standard digital library make it possible to synthesize the most parts of the VCO-based Nyquist ADC, greatly reducing the design costs. At Nyquist input frequency and a 5 MS/s sampling rate, a signal-to-noise and distortion ratio of 56.7 dB and a spurious-free dynamic range of 72.2 dB are achieved, respectively. The core occupies $450\,\, {\mu }{ \text{m}} {\times } {280}\,\, {\mu }\text{m}$ .

A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping

In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order $\Delta \Sigma $ modulators. A first advantage of our approach is that it unveils systematic error components not described by the equivalence with a conventional $\Delta \Sigma $ modulator. A second advantage is that, by a proper selection of the pulses generated by the PFM, we can theoretically construct an open loop VCO-ADC with an arbitrary noise shaping order. Unfortunately, with the exception of the first-order noise shaping case, the required pulse waveforms cannot easily be implemented on the circuit level. However, we describe circuit techniques to achieve a good approximation of the required pulse waveforms, which can easily be implemented by practical circuits. Finally, our approach enables a straightforward description of multistage $\Delta \Sigma $ modulator architectures, which is an alternative and practically feasible way to realize a VCO-ADC with extended noise shaping.

A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS

A Nyquist voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) architecture is proposed for ac-coupled systems that are commonly used in high-speed wireline and wireless communications. The proposed ADC utilizes a built-in high-pass filter as an analog differentiator, replacing the digital differentiator in conventional oversampling VCO-based ADCs. As a result, it avoids quantization noise shaping and achieves wideband Nyquist operation, inherited first-order antialiasing filtering, and improved VCO linearity without calibration. Analyses and simulations of various circuit nonidealities’ effects on the proposed ADC architecture are also provided. The ADC prototype achieves a peak SNDR of 34 dB and an SFDR of 50 dB with over 400-MHz input bandwidth and a sampling rate of 800 MS/s. It occupies an active area of 0.01 mm2 and consumes 3.62 mW in 65-nm CMOS.

Mitigation of Sampling Errors in VCO-Based ADCs

Voltage-controlled-oscillator-based analog-to-digital converter (ADC) is a scaling-friendly architecture to build ADCs in fine-feature complimentary metal-oxide-semiconductor processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared with a custom design flow. However, robust architectures and circuit techniques that reduce the dependence of performance on component accuracy are required to achieve good performance while designing converters with low accuracy components like standard cells in deeply-scaled processes. This paper investigates errors resulting from the sampling of a fast switching multi-phase ring oscillator output. A scheme employing ones-counters is proposed to encode the sampled ring oscillator code into a binary representation, which is resilient to a class of sampling induced errors modeled by the temporal reordering of the transitions in the ring. In addition to correcting errors caused by deterministic reordering, proposed encoding suppresses conversion errors in the presence of arbitrary reordering patterns that may result from automatic place-and-route in wire-delay dominated processes. The error suppression capability of the encoding is demonstrated using MATLAB simulation. The proposed encoder reduces the error caused by the random reordering of six subsequent bits in the sampled signal from 31 to 2 LSBs for a 31-stage oscillator.

Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC

Non-linear voltage-to-frequency characteristic of a voltage-controlled oscillator (VCO) severely curtails the dynamic range of analog-to-digital converters (ADCs) built with VCOs. Typical approaches to enhance the dynamic range include embedding the VCO-based ADC in a $\Delta\Sigma$ loop or to post-process the digital data for calibration, both of which impose significant power constraints. In contrast, in this work the VCO-based ADC is linearized through a filtered dithering technique, wherein the VCO-based ADC is used as a fine stage that processes the residue from a coarse stage in a 0–1 MASH structure. The proposed filtered dithering technique conditions the signal to the VCO input to appear as white noise thereby eliminating spurious signal content arising out of the VCO nonlinearity. The work resorts to multiple other signal processing techniques to build a high-resolution, wideband prototype, in 65 nm complementary metal-oxide semiconductor (CMOS), that achieves 10 effective number of bits (ENOB) in digitizing signals with 50 MHz bandwidth consuming 8.2 mW at a figure of merit (FoM) of 90 fJ/conv.step.

A low-power time-domain VCO-based ADC in 65 nm CMOS

A low-power, high-FoM (figure of merit), time-domain VCO (voltage controlled oscillator)-based ADC (analog-to-digital converter) in 65 nm CMOS technology is proposed. An asynchronous sigma—delta modulator (ASDM) is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR (exclusive-OR) gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic-distortion-cancellation technique to its transconductance stage, which increases the SNDR (signal to noise and distortion ratio) performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO's V—F (voltage to frequency) conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC's low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.

Investigation of voltage-controlled oscillator circuits using organic thin-film transistors (OTFT) for use in VCO-based analog-to-digital converters

A VCO-based ADC is a time-based ADC architecture that is highly digital with regard to its composition. In this paper, we analyze the performance of an organic voltage-controlled oscillator (VCO) employing different delay elements and investigate their suitability for use in a VCO-based analog-to-digital converter (ADC). An equation to calculate the theoretical limit of the resolution of the VCO-based ADC from the voltage versus frequency characteristics of the VCO was formulated. Using this equation we analysed various VCO architectures to realize the VCO-based ADC. We also investigated the impact of jitter and 1/f noise on the performance of the ADC. We have employed a ring oscillator based VCO in our design. The investigated single-ended delay elements were analyzed with respect to the linearity in their voltage versus frequency characteristics. This measure of linearity governs the resolution of the VCO and the VCO being the critical part of a VCO-based ADC, determines the maximum possible resolution of the whole VCO-based ADC. The resolution of all the investigated delay cells were calculated. Based on these results it was found out that the diode-load inverter delay cell is the most promising option to realize the VCO-based ADC. For such a VCO-based ADC using diode-load inverter delay stages, the measured results show that a maximum possible resolution of 5.8 bits can be achieved. In addition to the diode-load inverter based VCO, we also measured the VCO circuit using cut-off load inverter delay stages. The OTFTs use poly-3-hexylthiophene (P3HT) as the P-type semiconductor. Furthermore, the circuits were fabricated in a clean-room process that is compatible with printing processes for mass production.