A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS

Abstract

A Nyquist voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) architecture is proposed for ac-coupled systems that are commonly used in high-speed wireline and wireless communications. The proposed ADC utilizes a built-in high-pass filter as an analog differentiator, replacing the digital differentiator in conventional oversampling VCO-based ADCs. As a result, it avoids quantization noise shaping and achieves wideband Nyquist operation, inherited first-order antialiasing filtering, and improved VCO linearity without calibration. Analyses and simulations of various circuit nonidealities’ effects on the proposed ADC architecture are also provided. The ADC prototype achieves a peak SNDR of 34 dB and an SFDR of 50 dB with over 400-MHz input bandwidth and a sampling rate of 800 MS/s. It occupies an active area of 0.01 mm2 and consumes 3.62 mW in 65-nm CMOS.