A Standard-cell Based A/D Converter with a Back-gate VCO and a Fat Tree Encoder

Abstract

Analog-to-digital converters (ADCs) using voltage-controlled oscillators (VCOs) digitize analog signals in the phase domain, requiring no analog comparators and resistor ladders. This VCO-based ADC can be implemented with only digital standard cells provided by process vendors to maximize the advantages of technology scaling and design automation. A conventional VCO-based ADC consisting of the standard cells consumes additional power consumption and operates at the limited sampling frequencies due to buffers or sense amplifiers, keeping the output amplitude of the VCO constant, and a phase detector based on counters, respectively. We present an ADC with a back-gate VCO and a phase detector consisting of NAND gates and a fat tree encoder. The VCO produces rail-to-rail output signals not depending on the input signals, requiring no buffers and amplifiers. The phase detector can operate at higher sampling frequencies than the ones based on counters. The proposed VCO-based ADC, designed in a 65-nm digital CMOS process, achieves an SNR of 57.9 dB, excluding harmonics, in 20-MHz bandwidth with a sampling frequency of 800 MHz and a power consumption of 2.7 mW on simulation. This results in the best FoM (105 fJ/step) among the previously reported VCO-based ADCs consisting of standard cells.