Mitigation of Sampling Errors in VCO-Based ADCs

Abstract

Voltage-controlled-oscillator-based analog-to-digital converter (ADC) is a scaling-friendly architecture to build ADCs in fine-feature complimentary metal-oxide-semiconductor processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared with a custom design flow. However, robust architectures and circuit techniques that reduce the dependence of performance on component accuracy are required to achieve good performance while designing converters with low accuracy components like standard cells in deeply-scaled processes. This paper investigates errors resulting from the sampling of a fast switching multi-phase ring oscillator output. A scheme employing ones-counters is proposed to encode the sampled ring oscillator code into a binary representation, which is resilient to a class of sampling induced errors modeled by the temporal reordering of the transitions in the ring. In addition to correcting errors caused by deterministic reordering, proposed encoding suppresses conversion errors in the presence of arbitrary reordering patterns that may result from automatic place-and-route in wire-delay dominated processes. The error suppression capability of the encoding is demonstrated using MATLAB simulation. The proposed encoder reduces the error caused by the random reordering of six subsequent bits in the sampled signal from 31 to 2 LSBs for a 31-stage oscillator.