Bulk-Input VCO-Based Sigma-Delta ADCs with Enhanced Linearity in 28-nm FD-SOI CMOS

Abstract

This paper investigates the use of the transistor threshold-voltage tuning feature available in 28-nm Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology in order to improve the performance of Voltage-Controlled Oscillators (VCOs) with application in Analog-to-Digital Converters (ADCs). Circuit techniques that exploit the benefits of the enhanced body-effect biasing tunnability are applied to the proposed VCO in order to improve its linearity, frequency range and robustness to technology-process variations with respect to conventional ring oscillators. The proposed circuit is applied to the design of a second-order ΣΔ ADC clocked at a configurable rate of 1-to-2 GHz. The ADC uses a multi-phase VCO-based front-end integrator as the only analog circuit, while the rest of its building blocks are digital circuits. Transistor-level simulations show that the presented techniques improve the linearity with respect to conventional VCO-based ΣΔMs, featuring 10-bit effective resolution within a 10-MHz signal bandwidth, with an estimated power consumption of 230μW.1