Valence-band Electron Tunneling Research Articles

Impact of strain on gate-induced floating body effect for partially depleted silicon-on-insulator p-type metal–oxide–semiconductor-field-effect-transistors

This work investigates impact of mechanical strain on gate-induced-floating-body-effect (GIFBE) for partially depleted silicon-on-insulator p-type metal–oxide–semiconductor field effect transistors (PD SOI p-MOSFETs). First part, the original mechanism of GIFBE on PD SOI p-MOSFETs is studied. The experimental results indicate that GIFBE causes a reduction in oxide electric field (Eox), resulting in an underestimate of negative-bias temperature instability (NBTI) degradation. This can be attributed to the electrons tunneling from the process-induced partial n+ poly gate and anode electron injection (AEI) model, rather than the electron valence band tunneling (EVB) widely accepted as the mechanism for n-MOSFETs. And then, the second part shows that the strained FB device has less NBTI degradation than the unstrained devices. This behavior can be attributed to the fact that more electron accumulation was induced by strain-induced band gap narrowing, reducing NBTI significantly.

Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- $k$ Control Dielectrics

In this paper, memory devices integrating a double layer of silicon nanocrystals (Si-ncs) as a trapping medium and a HfAlO-based control dielectrics are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared with the single Si-nc layer devices, without introducing anomalies on the charging dynamics. Then, we also evaluate the potential use of a hybrid Si-nc double-layer/SiN layer charge trapping stack. These devices show a good memory window in a Fowler-Nordheim (FN)/FN mode and a good retention (>; 3 V after ten years) with small activation energy (0.35 eV up to 200 °C), thus showing promise for future high-temperature memory applications. A model implying valence-band electron tunneling and a floating-gate-like approximation is used to explain the memory window improvement of the Si-nc double-layer memory devices.

Characteristics of a high temperature vertical spin valve

We demonstrate high temperature electrical spin injection and detection in degenerately p-doped GaAs in vertical spin valves using valence band electron tunneling. The maximum measured magnetoresistance at 10 and 300 K is 40% and ∼1%, respectively. Spin relaxation in these devices was found to be relatively insensitive to temperature (T) for T>125 K. The spin injection and detection efficiencies are mostly dominated by the ferromagnetic contact polarization and spin independent transport at the ferromagnet/semiconductor interface.

On the Origin of Hole Valence Band Injection on GIFBE in PD SOI n-MOSFETs

This letter systematically investigates the mechanism of gate-induced floating-body effect (GIFBE) in advanced partially depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistors. Based on different operation conditions, we found that the hole current collected by the body terminal is strongly dependent on electrons in the inversion layer under a source/drain ground. This implies that GIFBE can be attributed to anode hole injection (AHI) rather than the widely accepted mechanism of electron valence band tunneling. Moreover, GIFBE was also analyzed as a function of temperature. The results provide further evidence that the accumulation of holes in the body results from the AHI-induced direct tunneling current from the gate.

Linear kink effect Lorentzians in the noise spectra of n- and p-channel fin field-effect transistors processed in standard and strained silicon-on-insulator substrates

The Lorentzian-like noise induced by Electron Valence Band (EVB) tunneling has been investigated in n- and p-channel multiple-gate field-effect transistors (MuGFETs), processed on silicon-on-insulator (SOI) and strained SOI (sSOI) substrates. The effect has been studied for different back-gate and front-gate biases and as a function of the device geometry. Similar as for wide fully depleted SOI transistors, this type of excess low-frequency noise is found when the back gate is biased in accumulation. However, it is shown that the characteristic time constant of the Lorentzian cannot be modeled assuming a uniform EVB tunneling current across the gate area of the MuGFETs. This indicates an impact of the three-dimensional nature of the device architecture on the so-called linear kink effects. In addition, it is demonstrated that the tensile strain in sSOI MuGFETs also yields a change in the Lorentzian parameters, associated with changes in the EVB tunneling current.

Temperature impact on the Lorentzian noise induced by electron valence-band tunneling in partially depleted SOI p-MOSFETs

In partially depleted (PD) silicon-on-insulator (SOI) MOSFETs with thin gate oxides, a particular effect named linear kink effect (LKE) occurs, which is due to the fact that the body potential is strongly affected by majority carriers injected in the body by the electron valence-band (EVB) tunneling through the ultra-thin gate oxide. This unexpected phenomenon induces a second peak in the transconductance gm curve and an excess Lorentzian noise in the low-frequency noise spectrum. A model based on RC filtered shot noise due to the EVB tunneling current and the forward current of the source-body junction was recently proposed at room temperature. In this work, the focus is on the temperature impact on the Lorentzian noise induced by valence-band electron tunneling in partially depleted SOI p-MOSFETs. For the first time, a Lorentzian noise filtered by the same RC network as the shot noise of the EVB tunneling current has been observed in the LKE operation at low temperature. It seems that the EVB tunneling current can also accompany an excess Lorentzian noise due to traps localized at the Si/gate oxide interface. A simple extension of the model developed by Lukyanchikova et al. is proposed and validated by experimental results from room temperature down to 80 K.

Excess Low-Frequency Noise in Ultrathin Oxide n-MOSFETs Arising From Valence-Band Electron Tunneling

Low-frequency flicker noise in analog n-MOSFETs with 15-/spl Aring/ gate oxide is investigated. A new noise generation mechanism resulting from valence-band electron tunneling is proposed. In strong inversion conditions, valence-band electron tunneling from Si substrate to polysilicon gate takes place and results in the splitting of electron and hole quasi-Fermi-levels in the channel. The excess low-frequency noise is attributed to electron and hole recombination at interface traps between the two quasi-Fermi-levels. Random telegraph signals due to the capture of channel electrons and holes is characterized in a small area device to support our model.

Valence-band electron-tunneling measurement of the gate work function: Application to the high-κ/polycrystalline-silicon interface

A technique is demonstrated to measure the band alignment between the silicon substrate and the gate electrode using the valence-band electron tunneling (VBET). When an n-channel metal-oxide-semiconductor field-effect transistor is biased in inversion the valence-band electron from the Si substrate can tunnel into the gate [A. Shanware, J. Shiely, H. Massoud, E. Vogel, K. Henson, A. Srivastava, C. Osburn, J. Hauser, and J. Wortman, Tech. Dig.-Int. Electron Devices Meet.1999, 815], depending on the overlapping of the density of states in the Si valence band and the gate. This technique is suitable to measure the band alignment between the silicon substrate and the gate electrode with any given gate dielectric, provided that both the gate and substrate leakages are dominated by direct tunneling. This technique has been applied to study the SiO2/polycrystalline-silicon (poly-Si) interface behavior in the presence of submonolayer traces of HfO2. The general applicability of VBET to arbitrary gate stacks is finally demonstrated with the HfSiON/poly-Si case.

Valence-band tunneling induced low frequency noise in ultrathin oxide (15Å) n-type metal-oxide-semiconductor field effect transistors

Low frequency flicker noise in n-type metal-oxide-semiconductor field effect transistors (n-MOSFETs) with 15Å gate oxide is investigated. A noise generation mechanism resulting from valence band tunneling is proposed. In strong inversion condition, valence-band electron tunneling takes place and results in the splitting of electron and hole quasi-Fermi levels in the channel. The excess low frequency noise is attributed to electron and hole recombination at interface traps between the two quasi-Fermi levels. Random telegraph signal in a small area device is characterized to support our model.

Soft breakdown enhanced hysteresis effects in ultrathin oxide silicon-on-insulator metal-oxide-semiconductor field effect transistors

The impact of oxide soft breakdown location on threshold voltage hysteresis in partially depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors with an ultrathin oxide (1.6nm) is investigated. Two breakdown enhanced hysteresis modes are identified. In a drain-edge breakdown device, excess holes result from band-to-band tunneling flow to the floating body, thus causing threshold voltage variation in drain bias switching. In contrast, in a channel breakdown device, enhanced threshold hysteresis is observed during gate bias switching because of increased valence band electron tunneling. Our findings reveal that soft breakdown enhanced hysteresis effect can be a serious reliability issue in silicon-on-insulator devices with floating body configuration.

Impact of gate tunneling floating-body charging on drain current transients of 0.10 μm-CMOS partially depleted SOI MOSFETs

In this paper, the impact of majority carriers introduced into the film by gate-body Electron Valence Band (EVB) tunneling in ultrathin gate oxide (2.5 nm) PD SOI MOSFETs is studied by analyzing “switch-off” drain current ( I d) transients measured with different front gate voltage steps and drain bias ( V d) conditions. A change in the I d transients shape from undershoot to overshoot is appreciated at low V d for sufficiently high “on” gate voltages, which enable gate-body EVB tunneling to introduce majority carriers into the film. The shape and the transition time of these EVB-induced I d overshoots have been found to be in good agreement with conventional (EVB-free) “switch-on”-type transients, which enable the extraction of the majority carrier recombination lifetime. It has been found that the magnitude of the EVB-induced I d overshoot decreases with increasing V d, finally resulting in an undershoot for sufficiently high V d. In order to characterize the effect of the charges introduced into the film during the different “switch-off” conditions, an effective gate voltage overdrive (Δ V geff) has been defined and extracted for all I d transients. It has been found that the transition from overshoot to undershoot can be explained by means of a body potential increase associated with the high V d condition, which results in a lower gate-to-film voltage drop and a reduced EVB majority carriers injection into the film.

Short-channel effects in the Lorentzian noise induced by the EVB tunneling in partially-depleted SOI MOSFETs

In this paper, the impact of the channel length ( L) on the parameters of the electron valence band (EVB) tunneling induced Lorentzian noise is described for partially-depleted (PD) silicon-on-insulator (SOI) MOSFETs. The Lorentzian time constant at a fixed gate overdrive voltage tends to increase for the shortest lengths studied, while the plateau amplitude of the current noise spectral density ( S I(0)) levels off at short L. A different behaviour is observed for the n- compared with the p-channel transistors, while a strong effect will be shown by the presence of a HALO implantation, used to control the short channel effect. It is demonstrated that the observations can be qualitatively explained by considering the Lorentzian noise as the result of the RC filtered shot noise accompanying the EVB tunneling current and the forward current of the source-body junction. For explaining the short-channel effects, it is pointed out that one should consider the lateral non-uniformity of the EVB tunneling current, which is related to the local variation of the threshold voltage V th.

Explaining the parameters of the electron valence-band tunneling related Lorentzian noise in fully depleted SOI MOSFETs

The behavior of the Lorentzian noise overshoot time constant /spl tau/ and plateau amplitude is investigated in fully depleted silicon-on-insulator MOSFETs with the back gate in accumulation. It is shown that /spl tau/ is identical for long-channel nand p-MOSFETs in the gate overdrive voltage range studied. For shorter lengths (L = 0.12 μm), a slight reduction of /spl tau/ for the p-MOSFETs and an increase for the short n-MOSFETs has been found. The observations will be explained by considering both the injection of majority carriers in the floating body through electron valence-band tunneling and the dynamic resistance of the source-body and gate-body junction.

Electron valence-band tunneling-induced Lorentzian noise in deep submicron silicon-on-insulator metal–oxide–semiconductor field-effect transistors

In this article, the impact of several electrical and technological parameters on a particular type of Lorentzian noise, occurring in deep submicron silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors with an ultrathin gate dielectric is described and a semi-empirical model is proposed that captures the main features of the experimental behavior. It is shown that the noise takes place in both n- and p-channel partially depleted SOI transistors. The excess Lorentzians are also found in the n-channel fully depleted devices studied, whereby the noise plateau amplitude [SI(0)] increases for a more negative back-gate bias, putting the back interface into stronger accumulation. The dependence of the characteristic time constant τ and SI(0) on transistor length, drain, front- and back-gate bias is reported, where from a first-order model is derived. The latter is based on the idea that the excess Lorentzian noise originates from filtered shot noise induced by majority carriers, that are injected in the floating body of the transistors by electron valence-band tunneling across the ultrathin (2.5 nm) gate oxide.

"Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs

In this paper, evidence will be provided for the existence of a new class of floating body effects, occurring in SOI and bulk MOSFETs in the linear operation regime and called here the linear kink effects (LKEs). It will be shown that for a sufficiently large front-gate voltage V/sub G/, the transconductance g/sub m/ exhibits a second peak, both for n- and p-channel devices. The effect is most pronounced for partially depleted (PD) n-MOSFETs or bulk MOSFETs at cryogenic temperatures. It occurs as well in fully depleted (FD) transistors, with the back-gate preferably biased into accumulation. Associated with the LKE in the drain current, there is a strong increase of the low-frequency noise spectral density S/sub I/. Similar as for the impact-ionization related noise overshoot, it is observed that the nature of the spectrum changes from 1/f-like to Lorentzian in the LKE region. It is finally shown that the switching off transients change their sign from negative to positive for V/sub G on/ above the LKE threshold, giving evidence for the presence of majority carriers in the film during the ON phase.

Hot-Carrier-Induced Degradation on 0.1 µm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor

Hot-carrier-induced degradation of partially depleted silicon-on-insulator (SOI) complementary metal-oxide-semiconductor field-effect-transistors (CMOSFET)s at various applied voltages and temperatures was investigated with respect to 0.1 µm body-contact (BC-SOI) and floating-body (FB-SOI) devices with 2 nm gate oxide. In our experiment, it is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. For FB-SOI nMOSFET maximum hot-carrier-induced degradation is inversely temperature dependent compared to BC-SOI nMOSFET. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition and temperature dependence of maximum hot-carrier-induced degradation are similar for both 0.1 µm SOI pMOSFETs.

Hot-carrier-induced degradation for partially depleted soi 0.25-0.1 μm CMOSFET with 2-nm thin gate oxide

Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 /spl mu/m with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 /spl mu/m FB-SOI pMOSFET is similar to that of the 0.1 /spl mu/m BC-SOI pMOSFET.

Improved model for the stress-induced leakage current in thin silicon dioxide based on conduction-band electron and valence-band electron tunneling

This article presents a detailed investigation on the stress-induced leakage current (SILC) conduction mechanism via conduction-band electron (CBE) and valence-band electron (VBE) tunneling in thin oxides. An improved SILC model that is able to reproduce the experimental SILC over a wide range of oxide fields, and yet give a realistic level of extracted neutral trap concentration, is proposed. Calculations performed with the improved SILC model suggest that SILC conduction via neutral traps is accompanied by energy relaxation (i.e., an inelastic mechanism), irrespective of the origin (i.e., whether CBE or VBE) of the tunneling species. For both CBE and VBE tunneling, inelastic tunneling with energy relaxation (Erelax) of 1.5 and 0.8 eV, was found to fit the experimental measurements well. These values of Erelax agree with those reported in the literature.

Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling

A semi-empirical model is proposed to quantify the tunneling currents through ultrathin gate oxides (1-3.6 nm). As a multiplier to a simple analytical model, a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), gate materials (N/sup +/, P/sup +/, Si, SiGe) and tunneling processes. Each coefficient of the correction function is given a physical meaning and determined by empirical fitting. This new model can accurately predict all the current components that can be observed: electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence hand (HVB) in dual-gate poly-Si/sub 1-x/Ge/sub x/-gated (x=0 or 0.25) CMOS devices for various gate oxide thicknesses. In addition, this model ran also be employed to determine the physical oxide thickness from I-V data with high sensitivity. It is particularly sensitive in the very-thin-oxide regime, where C-V extraction happens to be difficult or impossible (because of the presence of the large tunneling current).

Characteristics of p-channel Si nano-crystal memory

In this work, the feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. By comparing the programming characteristics of devices with nano-crystals and devices without nano-crystals, the role of dots as storage node is presented. The programming and erasing mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. In case of erasing, the electron tunneling occurs from either the conduction band or the valence band. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.