Use Of Hardware Description Languages Research Articles

Generation of logic designs for efficiently solving ordinary differential equations on field programmable gate arrays

AbstractOrdinary differential equations can be used to describe simulation models. As such, solving these equations is an important task in the high performance computing (HPC) domain. Field programmable gate arrays (FPGAs) are a promising platform, expected to be usable as efficient accelerators for such computations. While the use of hardware description languages (HDLs) can produce very efficient logic designs, their unique concept is hard to adopt for scientists and software engineers. High‐level synthesis (HLS) tools promise faster development, but bear the risk of lower performance and increased resource consumption of the final design. But even when using HLS tools the user still requires specialized knowledge about FPGAs and circuit design. In order to reach a wide adoption of FPGAs in HPC applications, a need for simple to use tools which enable performant designs was identified. This article proposes a framework that is able to automatically generate specific and optimized solver logic from easy to handle configuration files. No manual development, nor special FPGA or programming knowledge is required. To measure the capability of the proposed tool, the performance was evaluated for different solver methods and compared with an alternative hand optimized HLS implementation. The logic generated by this improved approach is up to 43 times faster than its hand optimized HLS counterpart, depending on the solution method.

Parallel Processing Algorithms of Ultrasound Images

With the rapid development of microelectronics technology, digital image processing technology has deepened our lives. In the past, image processing mostly used software processing. Due to the large number of processing algorithms and the complexity of the algorithm, it could not meet the real-time requirements. Therefore, this paper proposes a method for parallel processing of ultrasound images based on fax by using a programmable logic device. Image fusion is to extract and synthesize complementary information from different sensors to obtain a more accurate, comprehensive and reliable description of the target or scene. The transmission of images and other images is achieved by the sound of various sensors, which is far from enough. This article presents the use of hardware description language to design image processing and drivers. The core of the print head, scan head and stepper motor can use the control interface to perform selective and parameter variable median filtering on the scanned graphic image through software. Edge sharpening, image field separation, binarization and other hardware processing are compared with a series of processing directly using software, and the optimal processing plan can be made well, and the processed image can be displayed and printed out on the. This design can produce practical results for designs in the fields of biomedicine, sports, and energy production.

A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC

Many digital signal processing applications require a channelizer capable of moving sections of the incoming spectrum to baseband quickly and efficiently with minimal spectral leakage and signal distortion. We report the design and implementation of a 4 GHz, 4096-branch, 8-tap, 2/1 oversampled polyphase channelizer implemented on a Xilinx RFSoC. The open-source design consists of only IP cores created using Vivado HLS (C++) and IP cores available in Vivado HLx and System Generator versions 2019.1+. The channelizer was tested using a PYNQ overlay and Jupyter Notebook (Python) hosted on the RFSoC embedded CPU. The design uses 24% of the LUTs, 9% of the DSP48s, and 11% of the BRAMs on the ZCU111 RFSoC evaluation board and meets timing constraints at 512 MHz. The oversampled polyphase channelizer suppresses spectral image components below -60 dB. This design provides the first example of an oversampled polyphase channelizer running on a system on a chip architecture created without direct use of hardware description language. The presented approach leverages high-level design tools and includes source code which can be readily adapted by other researchers and development teams without the need for specialist knowledge in high-performance FPGA design.

A methodology to standardize the development of FPGA-based high-performance DAQ and processing systems using OpenCL

Abstract The development of high-performance data acquisition (DAQ) and processing systems is crucial for the next-generation diagnostics used in big science experiments. In the ITER experiment, the instrumentation, control hardware, and software architecture selected for this type of application is called a fast controller. The core element of a fast controller is a chassis based on the use of the PCIe eXtension for Instrumentation (PXIe) or Micro Telecommunication Computing Architecture (MTCA). This paper presents a software framework named IRIO-OpenCL that was developed using the ITER CODAC Core System (CCS) Linux-based distribution, oriented toward the development of field-programmable gate array (FPGA)-based DAQ systems using OpenCL. State-of-the-art DAQ-FPGA systems are developed using hardware description languages (HDLs). The approach used in IRIO-OpenCL simplifies DAQ to enable the user to write C-like processing algorithms with OpenCL, minimizing the use of HDLs. The software has been implemented in C++ following ITER’s Nominal Device Support v3 (NDSv3) model that abstracts and generalizes the development of software device drivers and simplifies the interface with the Experimental Physics and Industrial Control System (EPICS). The framework has been validated in an ITER fast controller including an MTCA.4 chassis with an advanced mezzanine card (AMC) module using an Arria 10 FPGA from Intel FPGA and an FPGA mezzanine card (FMC) DAQ module from Analog Devices. The developed application solves the DAQ and processing problems associated with the neutron flux measurement and achieves a sampling rate of 1 GS/s using approximately 40 % of the FPGA resources. The methodology proposed in this paper reduces the development time of these systems while maintaining high performance.

АНАЛИЗ СРЕДСТВ И ТЕХНОЛОГИЙ РАЗРАБОТКИ FPGA КАК СЕРВИС

This article has analyzed the most effective integrated development environments from leading programmable logical device (PLD) manufacturers. Heterogeneous calculations and the applicability of a general approach to the description of hardware accelerator designs are considered. An analytical review of the use of the OpenCL language in the construction of high-performance FPGA-based solutions is performed. The features of OpenCL language usage for heterogeneous computing for FPGA-based accelerators are discussed. The experience of a unified description of projects for solutions based on CPU, GPU, signal processors and FPGA is analyzed. The advantages of using such a description for tasks that perform parallel processing are shown. Differences in productivity and labor costs for developing FPHA systems with parallel data processing for hardware description languages and OpenCL language are shown. The results of comparing commercially available solutions for building services with FPGA accelerators are presented. The advantages of the Xilinx platform and tools for building an FPGA service are discussed. The stages of creating solutions based on FaaS are proposed. Some FaaS related tasks are listed and development trends are discussed. The SDAccel platform of the Xilinx SDx family is considered, as well as the possible role of these tools in creating the FPGA computing platform as a service. An example of using SDAccel to develop parallel processing based on FPGA is given. The advantages and disadvantages of the use of hardware description languages with such design automation tools are discussed. The results of comparing the performance of the simulation speed of the system described with the use of programming languages and hardware description languages are presented. The advantages of modeling complex systems are discussed, especially for testing solutions involving the processing of tens of gigabytes of data and the impossibility of creating truncated test sets. Based on practical experience, the characteristics of development environments, including undocumented ones, are formulated.

FPGA Implementation of Adaptive Neuro-Fuzzy Inference Systems Controller for Greenhouse Climate

This paper describes a Field-programmable Gate Array (FPGA) implementation of Adaptive Neuro-fuzzy Inferences Systems (ANFIS) using Very High-Speed Integrated Circuit Hardware-Description Language (VHDL) for controlling temperature and humidity inside a tomato greenhouse. The main advantages of using the HDL approach are rapid prototyping and allowing usage of powerful synthesis controller through the use of the VHDL code. The use of hardware description language (HDL) in the application is suitable for implementation into an Application Specific Integrated Circuit (ASIC) and Field tools such as Quartus II 8.1. A set of six inputs meteorological and control actuators parameters that have a major impact on the greenhouse climate was chosen to represent the growing process of tomato plants. In this contribution, we discussed the construction of an ANFIS system that seeks to provide a linguistic model for the estimation of greenhouse climate from the meteorological data and control actuators during 48 days of seedlings growth embedded in the trained neural network and optimized using the backpropagation and the least square algorithm with 500 iterations. The simulation results have shown the efficiency of the implemented controller.

Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code

Deep submicrometer devices are expected to be increasingly sensitive to physical faults. For this reason, fault-tolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important advantages with regard to other techniques. First, as this type of techniques can be applied during the design phase of the system, they permit reducing the time-to-market. Second, they present high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high fault modeling capability. However, implementing automatically these techniques in a fault injection tool is difficult. Especially complex are the insertion of saboteurs and the generation of mutants. In this paper, we present new proposals to implement saboteurs and mutants for models in VHDL which are easy-to-automate, and whose philosophy can be generalized to other hardware description languages.

The Use of Hardware Description Languages in the Development of Microelectromechanical Systems

We describe how hardware description languages (HDLs) can be used to support the design and simulation of systems incorporating components interacting in multiple energy domains. This methodology encourages emphasis on higher-level system design while providing performance targets for lower-level component design. It can also be made independent of the actual simulation engine (special-purpose mixed domain simulators or separate simulators for different energy domains). This approach supports modular, hierarchical design and allows strategies such as rapid prototyping and component reuse to be applied to multidomain systems, thus speeding the development of such systems for commercial use.

Fast VLSI arithmetic algorithms for high-security elliptic curve cryptographic applications

We propose new methods for calculating fast VLSI arithmetic algorithms for secure data encryption and decryption in the elliptic curve cryptosystem (ECC), and also verify the proof-of-concepts by numerical expressions and through the use of HDL (hardware description language). We have developed a fast finite field multiplier that utilizes a new concept, and a finite field divider with an improved internal structure, as well as a novel fast algorithm for calculating kP, which is the most time-consuming operation in the ECC data encryption scheme. The proposed multiplier features a higher throughput per cost ratio than any other existing Galois field (GF) multiplier that can be used in the large prime finite field. Furthermore, our improved divider shows better extensibility. The developed algorithm for point multiplication decreases the steps required for iteration by half compared to that of the traditional double-and-add algorithm. It also reduces the number of field multiplications by about 19% and that of field divisions by about 9%.

From AHPL to VHDL: a course in hardware description languages

As the size and complexity of digital systems increase, more CAD tools are introduced in the hardware design process; a recent addition to this process is the use of hardware description languages (HDLs). Historically, HDL-based design courses have been taught mostly at the graduate level. Undergraduate courses have mainly emphasized the principles of digital systems design, at both the logic and architectural levels. The laboratory component of these courses often introduces the students to graphical design capture tools and their associated simulators. However, within the past few years industry has been moving away from graphical design captures and is more openly adopting HDL-based design methodologies. Based on these industry shifts, one can easily conclude that HDLs are becoming an integral part of the design automation environments; this in turn requires the updating of the curricula, either by incorporating new courses or by updating existing ones. Specifically, courses that introduce undergraduates to HDLs in general and a standard language such as VHDL or Verilog are becoming essential in preparing future engineers. This paper discusses an HDL-based design course offered at Northern Arizona University (NAU). The course is used as a vehicle to introduce NAU students to the underlying concepts behind modeling, simulating, and verifying-digital systems design using hardware description languages.

Design methodologies based on hardware description languages

In this paper, we are presenting the basic methodology to be used in the design of a digital system, based on the use of hardware description languages. The most important stages of the design flow and the computer-aided design tools involved are presented, from the initial specification to the final implementation. The design flow described in the paper is based on a top-down approach, as this is the methodology currently used for most of the digital systems to face the current system complexity. Although all the concepts and methods are feasible for any kind of digital electronic system, application-specific integrated circuits are, in particular, considered as an application example in the paper. Most of the examples shown are written in VHSIC HDL, as it is an IEEE Standard and is one of the most commonly used.

Hardware compilation: translating programs into circuits

Automatically translating a program specified in a programming language into a digital circuit is an idea of long standing interest. Thus far, the concept has appeared to be an uneconomical method of largely academic, but hardly practical interest. It has therefore not been pursued with vigor and consequently has remained an idealist's dream. With the increasing use of hardware description languages, however, it has become evident that hardware and software design share several traits. Hardware description languages let circuit specifications assume textual forms like programs, replacing traditional circuit diagrams with text. Increased interest in hardware compilation is largely due to the advent of large scale programmable devices. These devices can be configured on the fly, and hence be used to directly represent circuits generated through a hardware compiler. The author argues that it is now conceivable that parts of a program could be compiled into instruction sequences for a conventional processor and other parts could be compiled into circuits to be loaded onto programmable gate arrays. He advocates the development of a single language that could compile parts of a program into instruction sequences for a conventional processor and other parts into circuits for programmable gate arrays. The author points out what is better left to software and what is best implemented in hardware (namely, parallelism). The goal is to achieve a better understanding of the several important aspects that hardware and software design share, which may well be expressed in a common notation.

Addressing design for testability at the architectural level

The increasing use of hardware description languages (HDL's) in VLSI design and the emergence of high-level test generation programs has led to an interesting problem. There is a need for design for testability (DFT) techniques that can be applied early in the design phase to improve the effectiveness of ATPG programs on hard-to-test circuits. By an early identification of hard-to-test areas of a circuit, testability can be inserted prior to logic synthesis. In this paper, we first present a comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits. Based on an evaluation of the results, we propose techniques to automatically extract information from the high-level circuit description that could improve the performance of both ATPG tools. An automatic DFT tool that utilizes VHDL descriptions of the circuit to make an intelligent selection of flip-flops for partial scan is then described. Results on six hard-to-test circuits show that very high fault coverages can be obtained by both a gate-level and a high-level test generator on these circuits after scan. With this detailed study we demonstrate that a DFT tool can make a more efficient and effective selection of partial scan flip-flops by exploiting the high-level circuit information. It can accurately predict the hard-to-test areas of a circuit. Significant improvements in fault coverage and ATPG efficiency, and speedups in ATPG time, can be obtained by a gate-level and a high-level test generator after high-level scan selection.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Engineering software-designing mixed-signal ICs

Problems confronting designers when they include both analog and digital components on the same substrate are described. The use of hardware description languages and physical design tools is discussed. Future directions for CAD tool development are indicated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Engineering software-more logic synthesis for ASICs

Computer-aided design (CAD) tools that reduce application-specific integrated circuit (ASIC) development time are examined. The use of hardware description languages to ease the data entry tasks of ASIC designers is discussed. Coupling logic synthesis tools to layout tools is considered. Limitations of logic synthesis are addressed, and some features of intelligent synthesis tools are described. >

An investigation of the performance of a distributed functional digital simulator

The increased use of Hardware Description Languages (HDLs) in the process of designing digital systems has spawned an increased interest in the development of simulation systems for these HDLs. Unfortunately, the size and complexity of most contemporary digital systems is such that obtaining meaningful HDL simulation results may require days or even weeks of processing time. Thus, there is a growing need to speed-up the HDL simulation of digital systems at all levels of design abstractions. One promising approach is to depart from the von Neuman style of computation and use a general-purpose mutiprocessor system to simulate digital systems. As part of the research supported by SIGDA/DATC Design Automation Graduate Scholarship, we implemented a prototype distributed multi-level functional HDL simulator. The technique that we use to speed-up simulation is based on the Virtual Time algorithm.