Upward Current Gain Research Articles

Hole-spreading effect on upward current gain in n-p-n transistors

The upward current gain and stored charge for future small-sized n-p-n transistors have been studied. Included is the effect of hole spreading from a narrow base region to a wide emitter region, whether buried layer or substrate. When base dimensions are comparable with or shorter than the hole diffusion length in the emitter, the hole current is concentrated near the fringe of the base so that the base current tends to be proportional to the base length instead of the base area. The same tendency appears regarding the stored charge in the emitter. Hence, the scaling down of lateral dimensions gives rise to a decline in the upward current gain and cutoff frequency. The calculations introduced here are in quite fair agreement with the observed base currents in sidewall base contact structure (SICOS) n-p-n transistors, where dimensions for the emitter-base junction are almost the same as for the collector-base junction.

Base resistance of I/sup 2/L structures: its determination and its influence on upward current gain

A sectionalized structure-oriented model is used for the description of the DC behavior of a multicollector integrated injection logic (I/SUP 2/L) gate. The model includes high-injection effects in the p-n-p transistor base and lateral base resistance in the n-p-n transistor. Methods for measuring the base resistance are outlined. The validity of the obtained model is demonstrated by measurement and simulation of two methods of measuring upward current gain.

Gate delays of InGaAs/InP heterojunction integrated injection logic

The delay time of an InGaAs/InP heterojunction bipolar transistor integrated injection logic gate is calculated as a function of the npn transistor upward current gain and for fan-outs of one and four. It is shown that intrinsic gate delays under 300 psec are possible with a fan-out of 4 for a gate designed with 3 µm design rules and having 0.5 µm npn and pnp base widths. Gate delays well under 100 psec are predicted for less conservative designs.

V-Bipolar Device Utilizing Built-in Stress Gradient

A new bipolar device utilizing built-in stress gradient caused by V-groove is proposed. The V-grooves are formed in the interdigital or stripe type transistors so that the band gap in the base becomes narrower than that in the emitter when compression is applied by bonding the pellets onto Cu headers because of thermal expansion difference. The band gap change caused by the V-groove is calculated. This band gap gradient greatly increases the downward and/or upward common emitter current gain. A preliminary experiment was performed with a specially arranged transistor stressed by a sapphire stylus. The upward current gain was increased by a factor of 1000 with stress.

A High Speed I2L 1K Static RAM with 20 ns Access Time

A new structure of I2L static memory cell is proposed to improve the writing characteristics. The cell is fabricated by the double diffused base technology. The downward current gain of the bit transistor has been successfully reduced by increasing the base width without influencing the upward current gain of the flip-flop transistor. As a result, a minimum write pulse width of 40 ns was obtained compared with 100–200 ns in the conventional structure. A static 1 K bits I2L RAM, which was developed by introducing the new structure cell, operated at an address access time of 20 ns and a write pulse width of 40 ns with a power dissipation of 350 mW at a supply voltage of 5 V.

Inverse current gain improvement of bipolar transistors by double-base diffusion

The double-base diffusion process is introduced and is experimentally shown to significantly improve the inverse or upward current gain of the n-p-n bipolar transistor. The technique consists of a deep p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> diffusion into an external base region of multicollector transistors forming a close-in collar around the intrinsic base of each transistor. This technique, together with the use of deep diffusion n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> guard rings around the complete unit cell, is shown to improve the inverse current gain significantly.

Characteristics of I2L at low current levels

The validity of the injection model is assessed in the low power range. Experimental evidence is given that the three base current components ( I_{nc}, I_{no} , and I p ) can be determined from a three-gate experiment. The results are explained from the underlying device physics. Experimental data are presented for the temperature dependence of the upward current gain.

The effect of base resistance of the vertical npn transistor in I2L structures

Expressions are derived for the lateral base current and for the base-emitter voltage by solving the differential equations obtained from a physical model of the base region of the vertical npn transistor. The theoretical and experimental results concur in showing that on the one hand the decrease of the upward current gain of the individual collectors at higher values of the collector current is due to the lateral voltage drop, and that high injection effects appear only for small values of current gain which have no practical importance. On the other hand the curves of current gain plotted against collector current show that the lateral voltage drop causes a point of inflexion followed by a maximum. This effect is evident at that collector nearest to the injector (or even at several such collectors, depending upon how many there are). Furthermore it is seen that the decrease of the current gain is almost entirely independent of the current gain of the intrinsic transistor.

I/sup 2/L current gain design

A DC model useful for I/SUP 2/L upward current gain (/spl beta//SUB /spl mu//) design is described. An expression for /spl beta//SUB /spl mu// is obtained in terms of model parameters which are related to device morphology. Design parameters are identified for a standard bipolar technology and a minimum geometry cell.

Role of the external n-p-n base region on the switching speed of integrated injection logic (I/sup 2/L)

Two-dimensional simulation and charge control principles have been applied to reveal the factors which determine the minimum delay of an integrated injection logic (I/SUP 2/L) gate, and experimental verifications are carried out. Using a numerical analysis this paper shows that important factors in improving the speed of an I/SUP 2/L gate are reducing the amount of minority charge stored in the external base of the n-p-n transistor and use of a heavily doped emitter. It is, therefore, necessary that the concentration in the external base is increased as high as possible and that the diffusion depth is controlled with good accuracy. Improvement in speed by a factor of 2 is experimentally realized as the simulation predicts. The heavily doped external base improves upward current gain and reduces base resistance, achieving a high fan-out capability.