A High Speed I2L 1K Static RAM with 20 ns Access Time

Abstract

A new structure of I2L static memory cell is proposed to improve the writing characteristics. The cell is fabricated by the double diffused base technology. The downward current gain of the bit transistor has been successfully reduced by increasing the base width without influencing the upward current gain of the flip-flop transistor. As a result, a minimum write pulse width of 40 ns was obtained compared with 100–200 ns in the conventional structure. A static 1 K bits I2L RAM, which was developed by introducing the new structure cell, operated at an address access time of 20 ns and a write pulse width of 40 ns with a power dissipation of 350 mW at a supply voltage of 5 V.