Unstable Bits Research Articles

CNT-PUFs: Highly Robust and Heat-Tolerant Carbon-Nanotube-Based Physical Unclonable Functions.

In this work, we explored a highly robust and unique Physical Unclonable Function (PUF) based on the stochastic assembly of single-walled Carbon NanoTubes (CNTs) integrated within a wafer-level technology. Our work demonstrated that the proposed CNT-based PUFs are exceptionally robust with an average fractional intra-device Hamming distance well below 0.01 both at room temperature and under varying temperatures in the range from 23 ∘C to 120 ∘C. We attributed the excellent heat tolerance to comparatively low activation energies of less than 40 meV extracted from an Arrhenius plot. As the number of unstable bits in the examined implementation is extremely low, our devices allow for a lightweight and simple error correction, just by selecting stable cells, thereby diminishing the need for complex error correction. Through a significant number of tests, we demonstrated the capability of novel nanomaterial devices to serve as highly efficient hardware security primitives.

PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing

With the rapid development of the Internet of Things (IoT), compute-in-memory (CIM) is a promising candidate for edge computing, which eliminates the need for frequent data transfer between the memory and processing units. On one hand, CIM provides an efficient approach to achieve deep neural network (DNN) inference; on the other hand, its security issues such as model leakage are ignored in most of state-of-the-art studies. In the resource-limited conditions, it is essential to develop a lightweight secure scheme for CIM without significantly sacrificing its performance. In this work, a physical unclonable function (PUF)-CIM macro based on static random access memory (SRAM) is proposed for lightweight model protection. An SRAM-based PUF extracts unique and stable keys from the mismatch of multirow discharge rate and further achieves zero bit error rate (BER) under temperature and voltage fluctuations by the on-chip masking technique. Besides, we propose a 10T SRAM bit cell to perform xor operation and multiply-and-accumulate (MAC) operation in the same cell, which avoids weight movement during encryption and decryption. The whole process including key generation, xor encryption, and ciphertext MAC operation has been realized. The test chip is designed and fabricated in a 55-nm CMOS process. Experimental results show that the proposed PUF with on-chip masking can provide zero unstable bits and BER under temperature and voltage variations. The proposed PUF-CIM achieves 96.20% inference accuracy in MNIST. Besides, it presents 93.35–121.38-TOPS/W energy efficiency and 1324.24-GOPS throughput. Compared with the normal CIM, the proposed PUF-CIM can enhance AI model security, only with accuracy loss of 1% and energy efficiency degradation of 16.1%.

A complex model of a drilling rig rotor with adjustable electric drive

A modified mathematical model of an asynchronous electric drive of the rotor – a drill string – a bit – a rock is considered and implemented, which develops and generalizes the results of previously performed studies. The model includes the following subsystems: a model of an asynchronous drive with vector control; a model of formation of the resistance moment at the bottom of the bit, taking into account the peculiarities of the interaction between the bit and the rock; a model of a multi-mass mechanical part that takes into account the deformation of the drill string; subsystem for the drilling rig energy-technological parameters formation. The integrated model makes it possible to calculate and evaluate the selected drilling modes, taking into account their electro-mechanical, energy and technological efficiency and the dynamics of drilling processes. The performed computer simulation of drilling modes confirmed the possibility of a stick-slip effect accompanied by high-frequency vibrations during bit stops, which may change the direction of rotation of the bit, its accelerated wear and unscrewing of the drilling tool. Long bit stops lead to a significant decrease in the average bit rotation speed, which can explain the decrease in the ROP and increase in energy consumption when drilling in the zone of unstable bit rotation. The model can be used as a base for further improvement of rotary drilling control systems.

A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C

In this work, a Physically Unclonable Function (PUF) based on an improved regulated cascode current mirror (IRCCM) is presented. The proposed IRCCM improves the loop-gain of the gain-boosting branch over the conventional RCCM PUF, thereby increasing the output resistance and amplifying the mismatches due to random variations. The introduction of an explicit reference current in the biasing branch of the IRCCM results in lower native unstable bits, good robustness against environmental variations and very stable power consumption. The proposed PUF has been validated through measurement results on a test-chip implemented in a 130 nm CMOS process. The PUF performance was measured for supply voltages between 0.6 and 1.2V, and temperatures ranging from 0 °C to 75 °C. A comparison against similar designs from the literature has shown that the proposed PUF exhibits state of the art performance with improved reliability under supply voltage variations.

Stabilizing Techniques for Secure On-chip Key Generation Based on RO-PUF

Based on intrinsic physical characteristics of devices, Physically Unclonable Functions (PUFs) provide the high reliability while maintaining the sufficient uniqueness. However, in the practical implementation based on PUFs, the extracted bit-string normally exhibits the unavoidable small fluctuation. Hence, PUFs can be used for the application of chip identification, but not suitable for the application that strictly requires an exact generated number. In this work, we propose several techniques to stabilize the generated value based on the existing Ring Oscillator (RO)-PUF circuit so that the stable unique number can be directly used for high-profile hardware security applications. In detail, we design a specialized on-chip key generation circuit that repeatedly samples the RO frequency values for statistical analysis and dynamically phases out the unstable bits, resulting in a unique and stable output bit-string. The experiments are conducted for the actual data measured from Xilinx Artix-7 FPGA devices. The generated key is proven to be relatively stable and can be readily used for the emerging security applications.

A Dual-Mode Polarization Image Sensor Design Based on In-Pixel Dual-Band Metal Wire Grid for Trustworthy Sensing

In this article, we present the design of an on-chip polarization image sensor with a hardware root of trust (RoT) for trustworthy sensing provided by an interconnection metal-wire-grid (MWG) structure using a standard complementary-metal-oxide-semiconductor (CMOS) process. The proposed MWG structure features dual operation modes, which are polarization image sensing mode at the visible spectrum and physical unclonable function (PUF) mode at the near-infrared spectrum. By integrating the MWG on top of the photo-sensing pixel, the corresponding photocurrent is read out with a mainstream three-transistor-active-pixel-sensor (3T-APS). Moreover, prototype chips are fabricated using a 65-nm 1P8M CMOS process to validate the proposed design. For the polarization mode at 630 nm, the extinction ratio (ER) is measured to be 17 dB. For the PUF mode at 875 nm, the averaged unstable bits and bit error rate (BER) of 15 test chips are reported to be 3.5% and 0.29%, respectively. The responses generated in the PUF mode of the fabricated sensor chips also passed the widely adopted National Institute of Standards and Technology (NIST) and the autocorrelation function (ACF) randomness tests.

A Dual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization

In this paper, we present a novel physical unclonable function (PUF) based on dual entropy sources of a 2-transistor voltage reference (2T-VR) and a four-stage diode-clamped comparator. Featuring excellent stability over wide range of supply voltage and temperature, the proposed 2T-VR is constructed with one native transistor plus one PMOS transistor that are compensated to minimize its temperature coefficient. Moreover, different from most previous PUF implementations where a digital comparator with offset-cancellation is needed for digitizing the mismatched voltages/currents from the prior entropy stage, in this work, the customized diode-clamped comparator’s offset is well-exploited as an additional entropy source, which can be superposed on the above 2T-VR-based entropy to significantly elevate the whole PUF structure’s reliability. Besides, a near zero-overhead in-cell entropy sign based stabilization (ESS) scheme is proposed to further enhance the reliability by stabilizing the scenario with the dual entropy sources having opposite signs. The designed dual-entropy-superposed PUF is fabricated using a 65-nm standard CMOS process, and its excellent randomness is validated using the widely-accepted National Institute of Standards and Technology (NIST) PUB 800-22/800-90B and autocorrelation function (ACF) test tools. With the test chips repeatedly challenged at normal condition up to 4000 times, the measured native bit error rate (BER) and unstable bits are reported to be 0.16% and 1.3%, respectively. Moreover, with the operating temperature changing from −50°C to 130°C and the supply voltage changing from 0.8 V to 1.4 V, the native BER’s VT sensitivities without stabilization are measured to be 0.195%/10°C and 0.651%/0.1 V, respectively, which can be further reduced by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> with the proposed ESS scheme applied.

Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique

This paper presents an ultra-small physical unclonable function (PUF) chip structure to protect data in compact IoT sensor devices. The proposed PUF has far fewer transistors and a reduced active area compared to the conventional strong PUF with multiple challenge response pairs (CRPs). According to the manufacturing process variations, the conventional SRAM-based PUF uses a switching transistor and a main transistor to implement multiple CRPs, whereas the proposed structure adds the function of a switching transistor to a single main transistor, controlling the body voltage to switch the transistor. This unified and simple PUF structure results in significant silicon area reduction. For a PUF with a 32-bit challenge, the number of transistors is significantly reduced by 40&#x0025;; the active area of the conventional structure is <inline-formula> <tex-math notation="LaTeX">$57.78~\mu m^{2}$ </tex-math></inline-formula> while the area of the proposed structure is <inline-formula> <tex-math notation="LaTeX">$36.4~\mu m^{2}$ </tex-math></inline-formula>. Overall, an active area reduction of 38&#x0025; is realized with the same number of CRPs. Here, we implemented an SRAM-based PUF system with a 32-bit challenge, a 1024-bit response, and 160 million CRPs. PUF core cell shows energy efficiency of 0.09 pJ/bit. The inter-Hamming distance is 48.89&#x0025;, while the intra-Hamming distance is 1.2&#x0025; after data post-processing, i.e., discarding unstable bits. A prototype chip is implemented in the 65nm CMOS process with a supply voltage of 1.2V. Compared to the prior arts, the proposed prototype is shown effective silicon area reduction while maintaining remarkable energy efficiency.

A Reconfigurable SRAM Based CMOS PUF With Challenge to Response Pairs

This paper presents a reconfigurable SRAM-based physically unclonable function (PUF) topology with multiple challenge-response pairs (CRPs) per cell. The proposed PUF structure enables a very large CRP space by connecting additional pull-up and pull-down paths to each SRAM cell. These alternate pathways to the supply rail and ground are activated by the challenge inputs, which effectively reconfigure the transfer characteristics of each cross-coupled inverter. A newly proposed response instability detector improves bit error rate (BER) performance by discarding unstable response. In addition, the proposed PUF adds indirect challenges by scrambling the responses using a Galois linear feedback shift register (LFSR). The proposed PUF can be applied to a wider range of applications as a CRP PUF because it has multiple CRPs in addition to the small area and fast operating speed, which are the advantages of the conventional SRAM structure. In order to verify the performance of the proposed architecture, a 32×32-bit reconfigurable SRAM PUF array with 32-bit challenge is implemented in a 65 nm CMOS process. Experimental results show a core area of 88.867 μ m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit, energy efficiency of 0.082 pJ/bit, and inter-chip Hamming distance (HD) of 48.93% across 40 chips. By applying an unstable bit discard (UBD) scheme, BER is improved from 13.7% to 0.9%. Compared to the state-of-the-art, the proposed PUF is shown to be highly competitive in area, throughput and energy efficiency.

Perturbed Adaptive Belief Propagation Decoding for High-Density Parity-Check Codes

Algebraic codes such as BCH code are receiving renewed interest as their short block lengths and low/no error floors make them attractive for ultra-reliable low-latency communications (URLLC) in 5G wireless networks. This article aims at enhancing the traditional adaptive belief propagation (ABP) decoding, which is a soft-in-soft-out (SISO) decoding for high-density parity-check (HDPC) algebraic codes, such as Reed-Solomon (RS) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and product codes. The key idea of traditional ABP is to sparsify certain columns of the parity-check matrix corresponding to the least reliable bits with small log-likelihood-ratio (LLR) values. This sparsification strategy may not be optimal when some bits have large LLR magnitudes but wrong signs. Motivated by this observation, we propose a Perturbed ABP (P-ABP) to incorporate a small number of unstable bits with large LLRs into the sparsification operation of the parity-check matrix. In addition, we propose to apply partial layered scheduling or hybrid dynamic scheduling to further enhance the performance of P-ABP. Simulation results show that our proposed decoding algorithms lead to improved error correction performances and faster convergence rates than the prior-art ABP variants.

A 354F2 Leakage-Based Physically Unclonable Function With Lossless Stabilization Through Remapping for Low-Cost IoT Security

A leakage-based physically unclonable function (PUF) is proposed to provide cost-effective security for Internet of Things (IoT) devices. By exploiting the exponential dependence of subthreshold leakage current on a transistor's threshold voltage variations, a response key bit is generated with only 354F2 silicon area. Moreover, to improve stability without discarding challenge-response pairs (CRPs), a novel lossless stabilization scheme called “remapping” is proposed. The proposed leakage-based PUF exhibited a 3.87% native unstable bit ratio (UBR) and 0.426% native bit error rate (BER). With the proposed remapping and 11-bit temporal majority voting applied, the BER and UBR are significantly improved to 47 and 538 ppm, respectively, achieving stability as high as a conventional trimming approach without any key losses.

A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise

In this paper, we present a fully reconfigurable resistive random access memory (RRAM) physical unclonable function (PUF) based on the truly random dynamic entropy of the ubiquitous jitter noise, which is intrinsically different from most previously demonstrated PUF implementations with semiconductor fabrication’s process variation as the static entropy source. In addition, the proposed RRAM PUF is operated by configuring the mainstream RRAM cells to either high resistance state (for ‘1’) or low resistance state (for ‘0’), according to the customized ring oscillator (RO) true random number generator’s digital output that is determined by the random jitter noise. By completely removing the need of dedicated split resistance circuitry (SRC) in existing RRAM PUFs, the proposed implementation is fully compatible with the SET/RESET operations of the RRAM array for mainstream memory applications, leading to minimized design overhead and enhanced reliability without SRC-caused error bits. Fabricated using 130 nm standard complementary-metal-oxide-semiconductor (CMOS) process plus post-processing dedicated to the RRAM devices, the proposed RRAM PUF cell features an ultra-compact footprint of $1.82~\mu \text{m}^{2}$ (i.e., 108 $F^{2}$ ), which is capable of generating ~107 PUF bits per cell due to the time-variant property of jitter noise and the full reconfigurability of the RRAM PUF. This significantly innovates all the previous weak PUF implementations based on the static entropy source of process variation, where the maximum bit number per PUF cell is always limited and fixed after the chip fabrication. Meanwhile, ultra-low native unstable bits of 0.28% and bit error rate (BER) per 10°C of 0.03% can be achieved for the fabricated RRAM PUF. Moreover, by passing the widely-adopted bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test under various VT conditions, the true randomness of the customized RO TRNG’ dynamic entropy is validated using 65 nm standard CMOS process. Compared with the state-of-the-art weak PUF implementations, the native unstable bits is improved by $5.36\times $ and the BER per 10°C is improved by $4\times $ , even under the widest operating temperature range from −50°C to 150°C.

An Ultracompact Switching-Voltage-Based Fully Reconfigurable RRAM PUF With Low Native Instability

In this brief, an ultracompact and highly reliable physical unclonable function (PUF) is presented based on the mainstream resistive random access memory (RRAM) devices. With the entropy originating from the switching voltage between the high-resistance state (HRS) and the low-resistance state (LRS), the proposed RRAM PUF can be generated during the RRAM's standard SET operation, leading to minimized design overhead. In addition, different from the previous implementations where the adopted RRAM PUF cells are dedicated to the “PUF” function, the proposed RRAM PUF is fully reconfigurable between the “PUF” function and the normal memory function. Moreover, the proposed implementation is validated using a standard 0.13-μm CMOS process plus customized postprocessing dedicated to RRAM devices. Featuring a normalized PUF cell area of 108F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the native instability (i.e., unstable bits) is measured to be as low as 0.28% at the normal condition. With the operating temperature varying from -50 °C to 150 °C and the supply voltage varying from 4 to 6 V, the averaged bit error rate (BER) is reported to be as low as 0.06% and 0.095%, respectively.

A 373-F² 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and VSS Bias-Based Dark-Bit Detection

This article presents a highly stable SRAM-based physically unclonable function (PUF) using enhancement–enhancement (EE)-structure bit cells for native stability improvement. The PUF bit cells are power-gated 2-D and are normally in the OFF state, which largely reduces power and is beneficial to attack tolerance. In addition, a dark-bit detection technique based on a lightweight integrated ${V}_{\text {SS}}$ -bias generator is implemented in order to screen out potentially unstable bit cells (dark bits) induced by supply voltage/temperature (VT) variations and other factors. Measured native bit error rate (BER) of prototype chips fabricated in 130-nm standard CMOS is 0.21% at 0.8 V and 23 °C, which is 14 $\times $ better compared with the conventional SRAM-based PUF. After masking the detected dark bits, no bit error (3339 bits $\times $ 500 evaluations) appeared at the worst VT corner across 0.8 to 1.4 V and −40 °C to 120 °C. This technique also eliminated all unstable bits in the accelerated aging test. Both the data before and after dark-bit masking have passed all applicable NIST SP 800–22 randomness tests. The measured operational energy at 0.8 V is 128 fJ/bit and the standby power is 0.44 pW/bit, thanks to the 2-D power-gating scheme. The nMOS-only bit cell is highly compact, with a normalized bit cell area of 373 F 2.

A Method to Utilize Mismatch Size to Produce an Additional Stable Bit in a Tilting SRAM-Based PUF

A new concept for Physical Unclonable Functions (PUFs), the Mirror PUF, is proposed. The Mirror PUF can be applied to existing preselected PUF circuits by post-processing the preselection test results and has the potential to double the number of effective bits, with no additional area at the bit-cell level. The Mirror PUF utilizes a preselection test, which measures the amount of mismatch within the PUF cell. This data is generally used to determine the mask for a conventional PUF. Here, it is used as an entropy source that is not correlated to the original response of the PUF. Bit-cells with low mismatch are considered as a ‘0’ and cells with high mismatch as a ‘1’. A systematic method is shown for identifying unstable bits in the Mirror PUF response. It classifies the cells to ‘low’, ‘medium’ and ‘high’ mismatch, such that medium mismatch bits are considered as unstable and masked from the response. The concept was applied to a 65nm Si implementation of the Capacitive Tilt PUF (Shifman et al., 2020). All of the unstable cells of the Mirror PUF, except for 0.03%, were identified and masked, with a worst-case corner Bit Error-Rate (BER) of only 2.35E-5 and 0.00026% erroneous responses across all corners. The application of the Mirror PUF to the Capacitive tilt PUF increased the number of stable response bits by 66%. No observable correlation was found between the responses of the original PUF and the Mirror PUF.

A 2 Bit/Cell Tilting SRAM-Based PUF With a BER of 3.1E-10 and an Energy of 21 FJ/Bit in 65nm

An SRAM-based Physical Unclonable Function (PUF) with two independent bits/cells is presented along with a tilting preselection test designed to identify all the unstable bits. Results of analysis of the Decision Voltage of the SRAM-based PUF cell indicate that in certain conditions, only the NMOS transistors in the cell impact its response, whereas the PMOS devices are in cutoff. Two pairs of NMOS transistors are inserted in the cell, each of which represents an orthogonal bit. The tilt test evaluates the internal mismatch within each of the NMOS pairs so that if it is insufficient, the resulting bit is considered unstable and masked from the PUF response. The cell demonstrated a highly competitive area of 1420F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per bit, a bit-error-rate (BER) of 3.1E-10, and a very low energy consumption of 21fJ/bit in 65nm. After preselection, the 2 bit/cell PUF exhibited a near-ideal inter-chip Hamming distance (49.5%) and percentage of ones (50.6%).

A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization

This article presents a reconfigurable physically unclonable function (PUF) design fabricated using 65-nm CMOS technology. A subthreshold-inverter-based static PUF cell achieves 0.3% native bit error rate (BER) at 0.062-fJ per bit core energy efficiency. A flexible, native transistor-based voltage regulation scheme achieves low-overhead supply regulation with 6-mV/V line sensitivity, making the PUF resistant against voltage variations. Additionally, the PUF cell is designed to be reconfigurable with no area overhead, which enables stabilization without redundancy on chip. Thanks to the highly stable and self-regulated PUF cell and the zero-overhead stabilization scheme, a 0.00182% native BER is obtained after reconfiguration. The proposed design shows 0.12%/10 {\deg}C and 0.057%/0.1-V bit error across the military-grade temperature range from -55 {\deg}C to 125 {\deg}C and supply voltage variation from 0.7 to 1.4 V. The total energy per bit is 15.3 fJ. Furthermore, the unstable bits can be detected by sweeping the body bias instead of temperature during enrollment, thereby significantly reducing the testing costs. Last but not least, the prototype exhibits almost ideal uniqueness and randomness, with a mean inter-die Hamming distance (HD) of 0.4998 and a 1020x inter-/intra-die HD separation. It also passes both NIST 800-22 and 800-90B randomness tests.

A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio

In this paper, we present a novel physical unclonable function (PUF) design based on cascode current mirror array. By using a single-stage cascode amplifier for each PUF cell, the output impedance can be significantly elevated. Compared with a traditional single-stage amplifier-based current-mode PUF, the proposed structure is capable of generating more polarized voltage value for the output node. With an additional digital buffer, the temporal noise can be well-suppressed, and a rail-to-rail digital output can be provided with high native reliability. Moreover, through operating the transistors at the subthreshold region, the overall power consumption can be dramatically reduced. Featuring a compact footprint of $3.23~\mu \text{m}^{2}$ (i.e. 764 ${F}^{2}$ ) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF’s uniqueness is measured with 10 chip prototypes and reported to be 49.94%. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50%, which can be further improved to 0.79% by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips’ reliability under varied operating temperature from −40 °C to 120 °C and supply voltage from 0.95 to 1.3 V. The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86% and 1.02%, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by $1.16\sim 4.29\times $ , with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered.

A 20F2 Area-Efficient Differential NAND-Structured Physically Unclonable Function for Low-Cost IoT Security

A differential NAND-structured physically unclonable function (PUF) with 20F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area per bit is proposed for cost-effective Internet of Things applications. With the area-efficient NAND-array structure, a key bit is generated from a pair of minimum-sized nMOS transistors by effectively amplifying threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) mismatch. By utilizing the near-threshold current of the examined transistors, high sensitivity to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variation, which is desired for stability, and faster operation than leakage current-based PUFs is achieved. An offset-compensated comparison scheme is provided to accurately determine the key value without bias. The proposed PUF achieves 0.06% BER and 0.53% unstable bits with TMV11 while reducing the area by an order of magnitude compared with state-of-the-art CMOS-based PUFs.

Physically Unclonable Functions Using Foundry SRAM Cells

This paper describes a low voltage physically unclonable function (PUF) implemented with SRAM circuits. The approach allows the use of foundry cells, which are used in this paper, and requires very minor modifications to standard SRAM arrays. The PUF functionality is designed into large 1M-bit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts. The low variability foundry process produces good PUF results, demonstrating that the approach should also be good on conventional processes, since greater mismatch should positively impact PUF performance as measured by code word stability. The impact of process corners is also experimentally determined. Unstable bits, which we attribute to random telegraph noise is shown to be at manageable levels. We describe the circuit operation, statistical behavior, and suggest helper data functions that allow operation without error correction. This is important since error correction necessarily allows some leakage of the underlying secret codes.