Abstract
An SRAM-based Physical Unclonable Function (PUF) with two independent bits/cells is presented along with a tilting preselection test designed to identify all the unstable bits. Results of analysis of the Decision Voltage of the SRAM-based PUF cell indicate that in certain conditions, only the NMOS transistors in the cell impact its response, whereas the PMOS devices are in cutoff. Two pairs of NMOS transistors are inserted in the cell, each of which represents an orthogonal bit. The tilt test evaluates the internal mismatch within each of the NMOS pairs so that if it is insufficient, the resulting bit is considered unstable and masked from the PUF response. The cell demonstrated a highly competitive area of 1420F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per bit, a bit-error-rate (BER) of 3.1E-10, and a very low energy consumption of 21fJ/bit in 65nm. After preselection, the 2 bit/cell PUF exhibited a near-ideal inter-chip Hamming distance (49.5%) and percentage of ones (50.6%).
Highlights
An SRAM-based Physical Unclonable Function (PUF) with two independent bits/cells is presented along with a tilting preselection test designed to identify all the unstable bits
If there is a correlation between the states, e.g., if for some of the cells the PMOS pair dictates the response, it is expected that the probability of equal responses is higher than the probability of opposite responses, and the average Hamming Distance (HD) is expected to be less than 50%
The PMOS devices associated with the SRAM latch may only exert a negligible impact on the total mismatch of the cell, depending on its decision voltage
Summary
PHYSICALLY Unclonable Functions (PUFs) are innovative primitives for purposes of authentication of an IC (Integrated Circuit), secure provisioning and secret key storage. A few of the recent PUF classes, such as leakage, intentional DRC (design rule checking) violations and oxide rupture, can provide an area or energy efficient PUF bit-cell [3][4] These architectures may show a high dependency on the manufacturing process and might not scale well across process corners, between technologies, or over the PUF lifetime. Some PUF works proposed to reduce the BER by generating a stable-unstable bits mask after evaluating the PUF multiple times either at the manufacturing time, or after the device boot [7]. The authors have demonstrated an improvement of nearly 2X to the area of the SRAM-based PUF by sharing some of the PUF transistors, such that two independent bits are generated by each cell [15].
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