Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique

Jae-Won Nam,Ju-Hyeok Ahn,Jong-Phil Hong

doi:10.1109/access.2022.3153359

Abstract

This paper presents an ultra-small physical unclonable function (PUF) chip structure to protect data in compact IoT sensor devices. The proposed PUF has far fewer transistors and a reduced active area compared to the conventional strong PUF with multiple challenge response pairs (CRPs). According to the manufacturing process variations, the conventional SRAM-based PUF uses a switching transistor and a main transistor to implement multiple CRPs, whereas the proposed structure adds the function of a switching transistor to a single main transistor, controlling the body voltage to switch the transistor. This unified and simple PUF structure results in significant silicon area reduction. For a PUF with a 32-bit challenge, the number of transistors is significantly reduced by 40%; the active area of the conventional structure is <inline-formula> <tex-math notation="LaTeX">$57.78~\mu m^{2}$ </tex-math></inline-formula> while the area of the proposed structure is <inline-formula> <tex-math notation="LaTeX">$36.4~\mu m^{2}$ </tex-math></inline-formula>. Overall, an active area reduction of 38% is realized with the same number of CRPs. Here, we implemented an SRAM-based PUF system with a 32-bit challenge, a 1024-bit response, and 160 million CRPs. PUF core cell shows energy efficiency of 0.09 pJ/bit. The inter-Hamming distance is 48.89%, while the intra-Hamming distance is 1.2% after data post-processing, i.e., discarding unstable bits. A prototype chip is implemented in the 65nm CMOS process with a supply voltage of 1.2V. Compared to the prior arts, the proposed prototype is shown effective silicon area reduction while maintaining remarkable energy efficiency.

Highlights

T HE rapidly expanding deployment of IoT devices to remote and isolated areas leaves sensors and edge routers vulnerable to physical security attacks
The existing SRAM-based physical unclonable function (PUF) with multiple challenge response pairs (CRPs) has the advantage of compactness, though with an increase in the number of CRPs
The cell of the proposed structure has an area of 36.4μm2(20.8μm × 1.75μm), and it achieves an active area reduction of 38% due to the reduced number of transistors

Summary

INTRODUCTION

T HE rapidly expanding deployment of IoT devices to remote and isolated areas leaves sensors and edge routers vulnerable to physical security attacks. We conducted research on a method to dramatically reduce the increase in chip area while maintaining large number of CRP and compensated for the structural disadvantages of the conventional SRAM-based PUF system by controlling the body voltage of the transistor. B. OPERATING PRINCIPLE OF THE CONVENTIONAL APPROACH Fig. 4 describes the operation principle of the existing SRAM-based PUF with multiple CRPs. Depending on the challenge, the operation characteristics of the inverter change for each inverter selected and the metastable point changes, resulting in different responses. The existing SRAM-based PUF with multiple CRPs has the advantage of compactness, though with an increase in the number of CRPs. a structure with a 32-bit challenge requires 80 transistors. The response is generated at the output terminal through the buffer in the PUF array

SYSTEM TIMING PLAN

MEASUREMENT RESULTS

CONCLUSION