Unsigned Numbers Research Articles

Analysis of modeled 3D solar magnetic field during 30 X/M-class solar flares

Using non-linear force free field (NLFFF) extrapolation, 3D magnetic fields were modeled from the 12-min cadence Solar Dynamics Observatory Helioseismic and Magnetic Imager (HMI) photospheric vector magnetograms, spanning a time period of 1 hour before through 1 hour after the start of 18 X-class and 12 M-class solar flares. Several magnetic field parameters were calculated from the modeled fields directly, as well as from the power spectrum of surface maps generated by summing the fields along the vertical axis, for two different regions: areas with photospheric |Bz|≥ 300 G (active region—AR) and areas above the photosphere with the magnitude of the non-potential field (BNP) greater than three standard deviations above |BNP|̄ of the AR field and either the unsigned twist number |Tw| ≥ 1 turn or the shear angle Ψ ≥ 80° (non-potential region—NPR). Superposed epoch (SPE) plots of the magnetic field parameters were analyzed to investigate the evolution of the 3D solar field during the solar flare events and discern consistent trends across all solar flare events in the dataset, as well as across subsets of flare events categorized by their magnetic and sunspot classifications. The relationship between different flare properties and the magnetic field parameters was quantitatively described by the Spearman ranking correlation coefficient, rs. The parameters that showed the most consistent and discernable trends among the flare events, particularly for the hour leading up to the eruption, were the total unsigned flux ϕ), free magnetic energy (EFree), total unsigned magnetic twist (τTot), and total unsigned free magnetic twist (ρTot). Strong (|rs| ∈ [0.6, 0.8)) to very strong (|rs| ∈ [0.8, 1.0]) correlations were found between the magnetic field parameters and the following flare properties: peak X-ray flux, duration, rise time, decay time, impulsiveness, and integrated flux; the strongest correlation coefficient calculated for each flare property was 0.62, 0.85, 0.73, 0.82, −0.81, and 0.82, respectively.

Study on Degenerate Stirling Numbers

In this paper, we consider various Stirling numbers of both kinds, including the unsigned degenerate Stirling numbers of the first kind, the degenerate Stirling numbers of the second kind, the unsigned degenerate r-Stirling numbers of the first kind and the degenerate r-Stirling numbers of the second kind. The aim of this paper is by using generating functions to further study explicit expressions, some identities and equivalent relations for those Stirling numbers.

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

This research paper investigates the influence of different initial design techniques on the area, timing, and power aspects of technology-mapped designs. As a practical case study, we undertake the design and analysis of a 32-bit arithmetic logic unit (ALU) utilizing two distinct adder approaches. The ALU, a fundamental component of all processors, comprises three major units: the Adder responsible for signed and unsigned number addition and subtraction, the Logic unit which handles bitwise logical operations, and the Shifter unit facilitates arithmetic and logical shift operations. The two adder designs are based on the ripple carry method (ALU_RCA) and the Sklansky method (ALU_SKL), respectively. The design and analysis process involved utilizing established toolsets from Cadence, including NCSIM for simulation and verification, RTL Compiler for logic synthesis, static timing analysis and power estimation, and SOC encounter tool for floorplanning and layout. Through this investigation, we aim to shed light on the varying performance implications of different initial design approaches in technology-mapped designs.

A local injective proof of log-concavity for increasing spanning forests

We give an explicit combinatorial proof of a weighted version of strong log-concavity for the generating polynomial of increasing spanning forests of a finite simple graph equipped with a total ordering of the vertices. In contrast to similar proofs in the literature, our injection is local in the sense that it proceeds by moving a single edge from one forest to the other. In the particular case of the complete graph, this gives a new combinatorial proof of log-concavity of unsigned Stirling numbers of the first kind where a pair of permutations is transformed into a new pair by breaking a single cycle in the first permutation and gluing two cycles in the second permutation, while all the other cycles are left untouched.

Normal ordering associated with λ-Stirling numbers in λ-shift algebra

Abstract It is known that the Stirling numbers of the second kind are related to normal ordering in the Weyl algebra, while the unsigned Stirling numbers of the first kind are related to normal ordering in the shift algebra. Recently, Kim-Kim introduced a λ \lambda -analogue of the unsigned Stirling numbers of the first kind and that of the r r -Stirling numbers of the first kind. In this article, we introduce a λ \lambda -analogue of the shift algebra (called λ \lambda -shift algebra) and investigate normal ordering in the λ \lambda -shift algebra. From the normal ordering in the λ \lambda -shift algebra, we derive some identities about the λ \lambda -analogue of the unsigned Stirling numbers of the first kind.

On ore-Stirling numbers defined by normal ordering in the Ore algebra

Normal ordering in the eyl algebra is related to the Stirling numbers of the second kind, while normal ordering in the shift algebra is related to the unsigned Stirling numbers of the first kind. The Ore algebra - this name was introduced recently by Patrias and Pylyavskyy - is an algebra closely related to the Weyl algebra and the shift algebra. We consider a two-parameter family of generalized Ore algebras which comprises all algebras mentioned by specializing the parameters suitably. Analogs of the Stirling numbers - called Ore-Stirling numbers - are introduced as normal ordering coefficients in the generalized Ore algebra. In the limit where one parameter vanishes they reduce to the Stirling numbers of the second kind or the unsigned Stirling numbers of the first kind. Choosing the parameters appropriately, a oneparameter family of Ore-Stirling numbers interpolating between Stirling numbers of the second kind and unsigned Stirling numbers of the first kind is found. Several properties of the Ore-Stirling numbers as well as the associated Ore-Bell numbers are discussed.

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two’s complement (B2C) and MUX circuits, while DesignII combines binary two’s complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-of-the-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.

A Fibonacci analogue of the two’s complement numeration system

Using the classic two’s complement notation of signed integers, the fundamental arithmetic operations of addition, subtraction, and multiplication are identical to those for unsigned binary numbers. We introduce a Fibonacci-equivalent of the two’s complement notation and we show that addition in this numeration system can be performed by a deterministic finite-state transducer. The result is based on the Berstel adder, which performs addition of the usual Fibonacci representations of nonnegative integers and for which we provide a new constructive proof. Moreover, we characterize the Fibonacci-equivalent of the two’s complement notation as an increasing bijection between ℤ and a particular language.

ULog: a software-based approximate logarithmic number system for computations on SIMD processors

This paper presents a new number representation based on logarithmic number system (LNS) called unsigned logarithmic number system (ulog), as an alternative to the conventional floating-point (FP) number format, to use in approximate computing applications. ulog is tailored for software implementation on commercial general-purpose processors, and uses the same dynamic range as conventional IEEE Standard FP formats to prevent overflow and underflow. ulog converts FP numbers to fixed-point numbers and uses integer operations for all computations. Moreover, vectorization and approximate logarithmic addition have been used to increase the performance of the software implementation of ulog. Then, we used different BLAS benchmarks to evaluate the performance of the proposed format than IEEE standard formats. 16- and 32-bit ulog improve the runtime than double-precision at most 70.26% and 46.36%, respectively. Besides, accuracy analysis of the ulog based on different logarithm bases showed that base 4 has the lowest error in most cases.

A power constrained approximate multiplier with a high level of configurability

Approximate computing helps tackle the challenges of future embedded and high-performance computing by using various methodologies. By increasing the volume of computations and limiting the power consumption, approximate computing can address these challenges in various demands. Approximate computing aims to achieve acceptable accuracy, rather than exact and correct results and can be used in error-tolerant applications to reduce hardware resources, delay, and most importantly power consumption. This paper introduces a new approximate multiplier, with a high degree of configurability, for unsigned numbers. It aims to reduce all hardware metrics besides keeping high accuracy. The proposed method offers well-optimized options in a power-accuracy tradeoff compared to the other configurable algorithm instances. In addition, it provides a wide range of options with power saving from 35% to 85% to satisfy most applications with a desirable power budget. Furthermore, the proposed approximate multiplier has been employed in Discrete Cosine Transform (DCT) applications.

New results on Bernoulli numbers of higher order

Let r be any positive integer. In this paper, we revisit explicit and recurrence formulas satisfied by the Bernoulli numbers Bn(r) of higher order r. By using the unsigned Stirling numbers, we give them new forms and a clearer description. The second part of this study consists of providing and proving analogues of Kummer congruences and a von Staudt–Clausen theorem for the numbers Bn(r)∕(rnr), as well as investigating their numerators. Moreover, we study the p-integrality of these numbers. In the third part of this paper, we construct a new family of Eisenstein series Ek(r)(z) whose constant terms are the numbers Bn(r)∕(rnr). We prove a congruence for these new Eisenstein series. This generalizes the classical von Staudt–Clausen’s and Kummer’s congruences of Eisenstein series. Our study leads to several applications in algebraic number theory.

Design and implementation of fast RBSD multiplier

In the developing world, we need to meet the high-speed requirements of users in chips. It has become a necessity to have faster and more efficient gadgets in all sectors which can work beyond our expectations and imaginations and give a better experience. So, for that we have designed a multiplier which is faster and can provide results precisely. In this paper we are using RBSD encodings which make multiplier faster by not doing carry propagations and thereby reducing delay for getting output. Redundant Binary Signed Decimals (RBSD) multipliers are designed in such a way that it reduces partial products in multiplication and thereby the multiplier is carry-free. The RBSD multiplier proposed in this paper can perform both signed and unsigned number multiplication. The proposed system is being implemented in VIVADO 2020.2 version in Verilog language. This paper is a comparative analysis with the existing model of RBSD multiplier.

A generator tool for Carry Look-ahead Adders (CLA)

A carry look-ahead adder (CLA) is a digital circuit which is used widely used in any electronic computational device to improve speed calculation by reducing the time required to define carry bits. Despite the fact that CLA is used massively in modern digital systems, there is no online tool to automatically generate the HDL description. For this reason we developed a cloud based tool to automate the design of optimized CLA and provide custom testbenches to verify their correctness for singed and unsigned numbers. It is also can be used by the students to create and understand deeply the way CLA works.

Resolving software interoperability issues of unsigned number and date-time precision using JADE framework system

Resolving software interoperability issues of unsigned number and date-time precision using JADE framework system

Resolving Software Interoperability Issues of Unsigned Number and Date-Time Precision Using JADE Framework System

Resolving Software Interoperability Issues of Unsigned Number and Date-Time Precision Using JADE Framework System

Fast signed multiplier using Vedic Nikhilam algorithm

Vedic algorithm is beneficial for the application in the design of high-speed computing and hardware. This study presents a fast signed binary multiplication structure based on Vedic Nikhilam algorithm. The authors explored the Nikhilam sutra for unsigned decimal numbers to both signed decimal and binary operands. The proposed multiplier leads to significant gains in speed by converting a large operand multiplication to small operand multiplication, along with addition. The proposed design is synthesised with Xilinx ISE 14.4 software and realised using different field programmable gate array devices. The efficiency of the proposed design depends on combinational delay, area and power. Moreover, the new multiplier architecture achieves speed improvement over prior design.

A note on degenerate r-Stirling numbers

The aim of this paper is to study the unsigned degenerate r-Stirling numbers of the first kind as degenerate versions of the r-Stirling numbers of the first kind and the degenerate r-Stirling numbers of the second kind as those of the r-Stirling numbers of the second kind. For the degenerate r-Stirling numbers of both kinds, we derive recurrence relations, generating functions, explicit expressions, and some identities involving them.

Configurable DSI partitioned approximate multiplier

Approximate computing has been considered for error-tolerant applications that can tolerate some loss of accuracy. It improves metrics such as dynamic power, delay, and area. Multipliers are key elements in arithmetic logic units and used in many applications such as Digital Signal Processing (DSP). Hence, it is vital to develop a robust strategy to take advantage of approximate computing in multipliers. In this paper, a novel algorithm has been presented for the approximate multiplication of unsigned numbers. The proposed approach is error-configurable and provides a trade-off between hardware resources, accuracy, delay, and power. In addition, it can be adjusted based on target systems or applications. The proposed method, compared to the accurate and other configurable algorithm instances, improves the metrics by using a low power configuration. Meanwhile, according to experimental results, the average error rates is 1.04% for 16-bit multiplication. The percentage of improvements for error, delay, area, and dynamic power of the proposed 16-bit multiplier are 0.02% to 16.71%, 23.8% to 70.6%, -11% to 34.1%, and 42.9% to 81.1%, respectively. Moreover, the proposed multiplier has been employed in Discrete Cosine Transform (DCT) applications and has obtained admirable outputs.

The r-central factorial numbers with even indices

In this paper, we introduce the r-central factorial numbers with even indices of the first and second kind as extended versions of the central factorial numbers with even indices of both kinds. We obtain several fundamental properties and identities related to these numbers. The connections between the new numbers and the Stirling numbers are presented. In addition, we give the probability distribution of the unsigned r-central factorial numbers with even indices. Finally, we consider the r-central factorial matrices and study some of their properties.

Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators

Multiplication is one of the most extensively used arithmetic operations in a wide range of applications, such as multimedia processing and artificial neural networks. For such applications, multiplier is one of the major contributors to energy consumption, critical path delay, and resource utilization. These effects get more pronounced in field-programmable gate array (FPGA)-based designs. However, most of the state-of-the-art designs are done for ASIC-based systems. Furthermore, a few field-programmable gate array (FPGA)-based designs that exist are largely limited to unsigned numbers, which require extra circuits to support signed operations. To overcome these limitations for the FPGA-based implementations of applications utilizing signed numbers, this letter presents an area-optimized, low-latency, and energy-efficient architecture for an accurate signed multiplier. Compared to the Vivado area-optimized multiplier IP, our implementations offer up to 40.0%, 43.0%, and 70.0% reduction in terms of area, latency, and energy, respectively. The RTL implementations of our designs will be released as an open-source library at https://cfaed.tu-dresden.de/pd-downloads.