A power constrained approximate multiplier with a high level of configurability

Abstract

Approximate computing helps tackle the challenges of future embedded and high-performance computing by using various methodologies. By increasing the volume of computations and limiting the power consumption, approximate computing can address these challenges in various demands. Approximate computing aims to achieve acceptable accuracy, rather than exact and correct results and can be used in error-tolerant applications to reduce hardware resources, delay, and most importantly power consumption. This paper introduces a new approximate multiplier, with a high degree of configurability, for unsigned numbers. It aims to reduce all hardware metrics besides keeping high accuracy. The proposed method offers well-optimized options in a power-accuracy tradeoff compared to the other configurable algorithm instances. In addition, it provides a wide range of options with power saving from 35% to 85% to satisfy most applications with a desirable power budget. Furthermore, the proposed approximate multiplier has been employed in Discrete Cosine Transform (DCT) applications.