Configurable DSI partitioned approximate multiplier

Abstract

Approximate computing has been considered for error-tolerant applications that can tolerate some loss of accuracy. It improves metrics such as dynamic power, delay, and area. Multipliers are key elements in arithmetic logic units and used in many applications such as Digital Signal Processing (DSP). Hence, it is vital to develop a robust strategy to take advantage of approximate computing in multipliers. In this paper, a novel algorithm has been presented for the approximate multiplication of unsigned numbers. The proposed approach is error-configurable and provides a trade-off between hardware resources, accuracy, delay, and power. In addition, it can be adjusted based on target systems or applications. The proposed method, compared to the accurate and other configurable algorithm instances, improves the metrics by using a low power configuration. Meanwhile, according to experimental results, the average error rates is 1.04% for 16-bit multiplication. The percentage of improvements for error, delay, area, and dynamic power of the proposed 16-bit multiplier are 0.02% to 16.71%, 23.8% to 70.6%, -11% to 34.1%, and 42.9% to 81.1%, respectively. Moreover, the proposed multiplier has been employed in Discrete Cosine Transform (DCT) applications and has obtained admirable outputs.