Design and implementation of fast RBSD multiplier

Abstract

In the developing world, we need to meet the high-speed requirements of users in chips. It has become a necessity to have faster and more efficient gadgets in all sectors which can work beyond our expectations and imaginations and give a better experience. So, for that we have designed a multiplier which is faster and can provide results precisely. In this paper we are using RBSD encodings which make multiplier faster by not doing carry propagations and thereby reducing delay for getting output. Redundant Binary Signed Decimals (RBSD) multipliers are designed in such a way that it reduces partial products in multiplication and thereby the multiplier is carry-free. The RBSD multiplier proposed in this paper can perform both signed and unsigned number multiplication. The proposed system is being implemented in VIVADO 2020.2 version in Verilog language. This paper is a comparative analysis with the existing model of RBSD multiplier.