Universal Logic Modules Research Articles

A “BILLIARDS” SIMULATION OF AN UNIVERSAL LOGIC MODULES BASED ON THE FREDKIN GATES FOR THE QUANT-UTING

In the wave of the green computing trend, research has recently intensified on the so-called adiabatic logic, reversible computing, which is supposed to be the basis of quantum computers and bring to a new level of computing power, combined with low power consumption. The basis of this logic is special reversible gates, for example, Fredkin’s gates. Reversibility is a one-to-one correspondence (bijection) between the inputs and outputs of circuits, which means, on the one hand, the possibility of total control of the results of calculations, and on the other hand, the possibility of returning the obtained "energy" quanta for the perform calculations to their source. This approach can significantly reduce the power consumption of computers, as well as increase the reliability of calculations. There are a lot of publications on this topic, however, the development of universal logic modules on such a basis has not been fully considered. The aim of the study is the development and modeling of universal logic modules based on the Fredkin element. In this case, the methods of logical synthesis of a reversible scheme based on a binary Fredkin element, modeling and analysis of billiard calculations are used. The article presents the proposed schemes of the decoder and multiplexer based on the Fredkin element, the "billiard" simulation. The practical significance of the study lies in the fact that the obtained universal logic modules can be used in the synthesis of binary reversible circuits, for example, FPGAs. The performed simulation can be used as examples in practical exercises in the discrete mathematics, mathematical logic, mathematical modeling, and circuitry disciplines.

An extended Green-Sasao hierarchy of canonical ternary Galois forms and Universal Logic Modules

A new extended Green-Sasao hierarchy of families and forms with a new sub-family for many-valued Reed-Muller logic is introduced. Recently, two families of binary canonical Reed-Muller forms, called Inclusive Forms (IFs) and Generalized Inclusive Forms (GIFs) have been proposed, where the second family was the first to include all minimum Exclusive Sum-Of-Products (ESOPs). In this paper, we propose, analogously to the binary case, two general families of canonical ternary Reed-Muller forms, called Ternary Inclusive Forms (TIFs) and their generalization of Ternary Generalized Inclusive Forms (TGIFs), where the second family includes minimum Galois Field Sum-Of-Products (GFSOPs) over ternary Galois field GF(3). One of the basic motivations in this work is the application of these TIFs and TGIFs to find the minimum GFSOP for many-valued input-output functions within logic synthesis, where a GFSOP minimizer based on IF polarity can be used to minimize the many-valued GFSOP expression for any given function. The realization of the presented S/D trees using Universal Logic Modules (ULMs) is also introduced, whereULMs are complete systems that can implement all possible logic functions utilizing the corresponding S/D expansions of many-valued Shannon and Davio spectral transforms.

A GA Based Simple and Efficient Technique to Design Combinational Logic Circuits Using Universal Logic Modules

A Genetic Algorithm based optimization technique for the design of combinational logic circuits using Universal logic Modules, 2-1 multiplexer or 2-1 Reed Muller block is proposed. In contrast to applying same select signals for all the units in a level of tree network in conventional methods, the proposed method allows any variable to be used as select signal to any unit in any level. In addition to the use of variables as select signals, the proposed method uses functions derived from previous level as select signal which is not the case in conventional methods. With this technique, complexity of the circuits is made lesser which leads to lesser power consumption, area and delay as compared to the current and conventional methods available in the literature. Standard Boolean functions are implemented to design circuits up to six variables and the results are validated with benchmark functions.

Methods of choosing universal logic modules for FPGAs and ASIC

A short review is given of structures of universal logic modules (ULMs) used by leading manufacturers of FPGAs and SASICs. A brief description is presented of the proposed approach to optimal selection of the design of ULMs. The results are given of numerical experiments on the selection of the ULM with the optimal number of inputs. The results have been obtained with the help of the software prototype developed to optimize the design of the ULM.

Single Core Hardware Module to Implement Boolean Function Classification Techniques

Problem statement: Boolean function classification plays an important role in the field like technology mapping for digital circuit design, function mapping for minimization and the development of universal logic modules. Approach: In this study, we present a single core hardware module to implement Boolean function classification techniques on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm was performed by incorporating Boolean function classification into Huffman coding. This allows compression that was more efficient because the data had been categorized and simplified before the encoding was done. Simulation, timing analysis and circuit synthesis were commenced to verify the functionality and performance of the designated circuits which supports the practicality, advantages and effectiveness of the proposed single core hardware implementation. Results: The result shows a higher compression ratio. The average compression ratio was 25-37.5% from numerous testing with various text inputs with a maximum clock frequency of 27.9 MHz. Conclusion: The hardware implementation demonstrated complete, correct functionality and met all the initial system requirements.

Simplified electronic signal processing in the small nuclear physics laboratory

Small nuclear physics laboratories of all kinds traditionally have processed the signals from radiation detectors with a variety of discrete NIM- or CAMAC-based electronic modules. The logic signals associated with signal processing are often passed through gate generators, coincidence modules, fan-in/fan-out modules, delay units, counters, and other assorted logic modules. These multi-component systems generate gates for acquisition systems, gates for specific linear electronics modules (ADCs and TDCs), or measure count rates and dead times. This can involve a significant number of individual modules each of which can be quite costly and each of which provides only limited functions. We describe here an upgrade to our acquisition system where all the needed logic functions are performed in just a single unit: a Universal Logic Module based on a Field Programmable Gate Array (FPGA) from JTEC Corporation. This module also contains flash memory that holds three separate configurations allowing for rapid changes from one electronics configuration to a different one. Both CAMAC and VME versions of the unit are available. The system described here is just one example of the huge variety of functionality that can be programmed into this single module. It can accommodate very complicated circuits and is easily reprogrammed. In the small nuclear physics laboratory the Universal Logic Module can save cost when upgrading systems and reduce the number of instances where one has an insufficient number of channels of a particular function.

Using decision diagrams to design ULMs for FPGAs

Many modern field programmable logic arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs such blocks, known as Universal Logic Modules (ULMs), have already been considered for application in FPGAs; we propose a new class of ULMs which is more useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on the BDD description of logic functions. We give an explicit construction of a three-input LUT replacement that requires only five programming bits, which is the optimum for such ULMs. A realistic size four-input LUT replacement is obtained which uses 13 programming bits.

Generalised hybrid arithmetic canonical expansions for completely specified quaternary functions

A novel representation of completely specified quaternary functions, called ‘hybrid arithmetic canonical expansion’ is shown. The new expansion is based on both standard and GF(4) algebra. The transform matrix of the expansion is defined by an arbitrary set of linearly independent functions in GF(4). The introduced expansion is generalised by applying to it the concept of polarity. The way of obtaining the coefficient vector of the expansion from some coefficient vector in known polarity is introduced. Generalised hybrid arithmetic polynomial expansions for known basis functions from quaternary Reed–Muller transforms are shown. The idea of binary and ternary independent function is extended to the quaternary case and the new expansion for such a transform matrix is also presented. The generalised hybrid arithmetic expansion is canonical for completely specified quaternary functions. Finally, implementation of the generalised hybrid arithmetic expansion in the form of a suitable universal logic module is introduced.

Constructing Reed-Muller universal logic module networks from Reed-Muller binary decision diagrams

This paper presents the Reed-Muller binary decision diagram (RMBDD), an alternative means of representing generalized Reed-Muller (GRM) expansions. Particular emphasis is placed on the use of ordered Reed-Muller binary decision diagrams (ORMBDDs) as tools for constructing minimal (sub-minimal) Reed-Muller universal logic module (RM-ULM) networks. Initially, the structure of ordered Reed-Muller binary decision trees (ORMBDTs) is described and rules for reducing their size are introduced. The physical implementation of reduced ordered Reed-Muller binary decision diagrams (RORMBDDs) as RM-ULM networks is then illustrated. Additionally, a heuristic technique for determining the ordering of variables in an ORMBDD is detailed.

Alternative algorithm for optimisation of Reed–Muller universal logic module networks

Reed-Muller universal logic modules (RM-ULMs) can be used as individual modules or as networks to implement RM functions of any number of variables. For a large RM expansion, it is generally more efficient to realise it using cascades of low-order RM-ULMs. A programmed algorithm for the optimisation of the number of modules at the sub-system level has already been published. In the paper an alternative algorithm is presented which performs similar optimisation of fixed-polarity generalised RM expansions but without the need to maintain a saved-branch counter and an input record. Also, whenever the number of piterms having the specific control-tuple-state exceeds two, it is not necessary for the algorithm to perform separate variable examinations. Consequently, the saving in computation time will be especially significant in RM expansions with large number of variables. The resulting algorithm is simple in structure and can be easily implemented using high-level languages such as C or Fortran.

Multiple-valued logic network using quantum-device-oriented superpass gates and its minimisation

A superpass-transistor (SPT) model is presented as a quantum-device candidate for future VLSI systems based on multiple-valued logic (MVL). A conceptual SPT structure based on the ideas of a lateral-resonant-tunnelling quantum-dot transistor (LQT) and a heterostructure FET is described. An important feature of the SPT is its capability of MVL signal detection and generation. A superpass gate (SP gate) corresponding to a single SPT is defined and is demonstrated to be a universal logic module for implementing highly compact multiple-valued VLSI systems. An algorithm suitable for synthesising minimal series-parallel SP-gate networks for MVL functions with many variables is proposed. The network allows both constants and variables as its pass inputs; accordingly, upsilon -subfunctions, where upsilon can be a constant or a variable, are defined. SP implicants, SP subimplicants and the consensus between SP subimplicants are also defined. The algorithm first generates all prime SP subimplicants from upsilon -subfunctions by using the consensus operation, then derives all prime SP implicants by using the implication operation, and finally selects an optimal set of prime SP implicants to cover the function by using existing methods.

Homogeneous computing structures over a finite field

The proposed technique representing a combinational circuit in the form of a homogeneous network can be used in the design of universal logic modules. The transition from the realization of one combinational circuit to another is accomplished by changing the set of 2n — 1 coefficients, where n is the dimension of the combinational circuit.

A method for minimization design of two-level logic networks using multiplexer universal logic modules

A decomposition approach of the combinational functions is discussed. A design method, by which the minimization or near minimization of two-level combinational network can be obtained, is presented for a combinational function realized by using multiplexer universal logic modules. Using the method, the automated synthesis of the combinational functions can be accomplished on a computer.

Reed-Muller universal logic module and its application to function realization

A structure device known as the Reed-Muller universal logic module (RM-ULM) is developed based on a theorem extended from Shannon's expansion theorem to modulo-2 logic. To realize Reed-Muller polynomials in fixed-polarity using RM-ULMs, the problem becomes one of minimization for multiple-output functions. An existing algorithm for minimization of RM polynomials in fixed polarity is modified and applied to the realization of switching functions using RM-ULMs.

Full-custom design of Reed-Muller universal logic modules

Abstract Reed-Muller universal logic modules (RM-ULMs) and the development of prototype modules using full-custom techniques are discussed. The design of two-to-one and four-to-one RM-ULMs using 1-5μm CMOS technology is described. Design procedures using CHIPWISE and the SPICE simulation results of the modules are outlined.

Reed-Muller universal logic module networks

The paper describes Reed-Muller universal logic modules (RM-ULMs) and their use for the implementation of logic functions given in Reed-Muller (RM) form. A programmed algorithm is presented for the synthesis and optimisation of RM-ULM networks. The level-by-level minimisation procedure is based on the selection of control variables at different levels with the aim of maximising the number of discontinued branches and hence minimising the number of modules required to implement a given function. The algorithm is programmed in Fortran and can be used to realise fixed-polarity generalised Reed-Muller (GRM) expansions of any polarity and any number of variables.

Methods for detection of some properties of multiple-valued functions

In the paper, methods are given for some symmetry properties: detection and functional decomposition of multiple-valued functions. Both methods are formulated using a matrix notation which enables the fast algorithms for their implementation to be disclosed. The problem of optimisation in logic design can be considered with respect to a number of different criteria. However, in general, all of them finally can be reduced to the minimisation of the cost and to the minimisation of the time. In a classical setting, these criteria are usually expressed by the number of components, or by the number of inputs in logical elements, and by the delay of signals in a logical network, i.e. by the number of levels in the network. The reduced price of electronic components, together with the advent of different ways of realisation of discrete functions (PLA, universal logic modules, ROM-realisation etc.) provide us with hardware capabilities of low cost and high performance. This implies a change in the optimisation criteria which now can be replaced by the requirements for reducing the size of the silicon area and for efficient testability. Also, these days, the optimisation problems in logic design are closely related to the minimisation of time and efforts, and hence the cost, needed for the implementation of the synthesis procedure, rather than with reducing the cost of hardware components. The parameters mentioned can be greatly reduced in cases where the realised discrete function possesses some characteristic properties. Therefore, the development of efficient methods for analysis of discrete functions is a very important task. In this paper we propose a method for symmetry detection and a method for functional decomposition of multiple-valued functions including Boolean functions as a particular example.

Automated synthesis of digital multiplexer networks

A programmed algorithm is presented for the synthesis and optimisation of networks implemented with multiplexer universal logic modules. The algorithm attempts level by level optimisation selecting the control variables that result in minimum number of continuing branches. Cascaded networks, if realisable, are always found and given preference over tree networks, though mixtures of cascade and tree configurations are permitted. The algorithm is programmed in Fortran and tested for single and double control variable modules. In theory, the program can be used for any number of variables for completely and incompletely specified functions.

Automated synthesis of combinational circuits by cascade networks of multiplexers

Knowledge of the advantages of realising VLSI circuits in cellular form have stimulated research in the synthesis of digital circuits by using cellular networks of suitable gates. The cascade network is a special kind of cellular form with a very simple interconnection structure. This paper is concerned with the synthesis of combinational circuits using a cascade of 2-input multiplexer units. A multiplexer unit has been taken as the building block because of its versatility and possibility of use as a universal logic module. Based on the characterising parameters called ‘ratio parameters’, an algorithm has been developed to synthesise a given Boolean function by a cascade of two input multiplexers, if realisable. The algorithm is easy to implement on a computer and a program implementing the algorithm in c-language has been developed, thereby allowing automated synthesis. This is essential when the complexity of the digital circuits is high. Both completely specified and incompletely specified functions have been considered.

Multivalued input, two‐valued output logical element as a two‐valued universal logic module

AbstractThis paper proposes to use a multiple‐valued (p‐valued) input, 2‐valued output logical element ((p, 2)‐logical element) for the construction of a 2‐valued ULM (Universal Logic Module). The (p, 2)‐logical element can conveniently be programmed to work as an expected 2‐valued logical function by appropriately selecting two input values among p values. The (p, 2)‐logical element as a ULM also has some preferable points such that the interconnections between ULM's can be decreased in VLSI, compared with the ULM in usual 2‐valued logic.